diff mbox

[U-Boot,5/5,v1] integrator: make flash writeable on boot

Message ID 1316332378-18521-1-git-send-email-linus.walleij@linaro.org
State Superseded
Headers show

Commit Message

Linus Walleij Sept. 18, 2011, 7:52 a.m. UTC
This reconfigures the EBI (External Bus Interface) on the
integrator so that chip select 1, handling the flash memory, is
set to writeable. Without this it is not possible for U-Boot to
access flash memory and it crashes on startup since CFI won't
work properly.

Since this is the first time we use the EBI, we create a header
file for its registers.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 board/armltd/integrator/integrator.c |   15 ++++++++
 include/arm-ebi.h                    |   62 ++++++++++++++++++++++++++++++++++
 2 files changed, 77 insertions(+), 0 deletions(-)
 create mode 100644 include/arm-ebi.h

Comments

Mike Frysinger Sept. 18, 2011, 8:26 a.m. UTC | #1
On Sunday, September 18, 2011 03:52:58 Linus Walleij wrote:
>  board/armltd/integrator/integrator.c |   15 ++++++++
>  include/arm-ebi.h                    |   62
> ++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 0
> deletions(-)
>  create mode 100644 include/arm-ebi.h

if the integrator board is the only one that cares about this header, then 
it's probably best to keep it in the board-specific dir rather than include/
-mike
Albert ARIBAUD Sept. 18, 2011, 10:15 a.m. UTC | #2
Hi Linus,

Le 18/09/2011 09:52, Linus Walleij a écrit :
> This reconfigures the EBI (External Bus Interface) on the
> integrator so that chip select 1, handling the flash memory, is
> set to writeable. Without this it is not possible for U-Boot to
> access flash memory and it crashes on startup since CFI won't
> work properly.

Do you mean that U-Boot writes to the flash at each boot on this board?

Amicalement,
Wolfgang Denk Sept. 18, 2011, 1:24 p.m. UTC | #3
Dear Albert ARIBAUD,

In message <4E75C4A4.20604@aribaud.net> you wrote:
> 
> Le 18/09/2011 09:52, Linus Walleij a =E9crit :
> > This reconfigures the EBI (External Bus Interface) on the
> > integrator so that chip select 1, handling the flash memory, is
> > set to writeable. Without this it is not possible for U-Boot to
> > access flash memory and it crashes on startup since CFI won't
> > work properly.
> 
> Do you mean that U-Boot writes to the flash at each boot on this board?

I think this is a misunderstanding of terms.  When we try to
identify the flash type and geomentry in the CFI driver, we do send
certain commands to the flash, and read the returned data.  This
"sending commands" includes write cycles to the flash address space,
so it is necessary that the memory controller setup allows write
cycles on the bus.

This does however NOT mean that any data are programmed into the
flash.

Best regards,

Wolfgang Denk
Albert ARIBAUD Sept. 18, 2011, 4:24 p.m. UTC | #4
Le 18/09/2011 15:24, Wolfgang Denk a écrit :
> Dear Albert ARIBAUD,
>
> In message<4E75C4A4.20604@aribaud.net>  you wrote:
>>
>> Le 18/09/2011 09:52, Linus Walleij a =E9crit :
>>> This reconfigures the EBI (External Bus Interface) on the
>>> integrator so that chip select 1, handling the flash memory, is
>>> set to writeable. Without this it is not possible for U-Boot to
>>> access flash memory and it crashes on startup since CFI won't
>>> work properly.
>>
>> Do you mean that U-Boot writes to the flash at each boot on this board?
>
> I think this is a misunderstanding of terms.  When we try to
> identify the flash type and geomentry in the CFI driver, we do send
> certain commands to the flash, and read the returned data.  This
> "sending commands" includes write cycles to the flash address space,
> so it is necessary that the memory controller setup allows write
> cycles on the bus.
>
> This does however NOT mean that any data are programmed into the
> flash.

Indeed, I had misunderstood the commit message. Apologies.

> Best regards,
>
> Wolfgang Denk

Amicalement,
Linus Walleij Sept. 19, 2011, 7:51 a.m. UTC | #5
On Sun, Sep 18, 2011 at 3:24 PM, Wolfgang Denk <wd@denx.de> wrote:

> I think this is a misunderstanding of terms.  When we try to
> identify the flash type and geomentry in the CFI driver, we do send
> certain commands to the flash, and read the returned data.  This
> "sending commands" includes write cycles to the flash address space,
> so it is necessary that the memory controller setup allows write
> cycles on the bus.

Yes that is exactly what happens. The integrator has some gate to
disallow any write cycles to CFI unless it's unlocked through the EBI.

Yours,
Linus Walleij
Linus Walleij Sept. 19, 2011, 7:54 a.m. UTC | #6
On Sun, Sep 18, 2011 at 10:26 AM, Mike Frysinger <vapier@gentoo.org> wrote:
> On Sunday, September 18, 2011 03:52:58 Linus Walleij wrote:
>>  board/armltd/integrator/integrator.c |   15 ++++++++
>>  include/arm-ebi.h                    |   62
>> ++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 0
>> deletions(-)
>>  create mode 100644 include/arm-ebi.h
>
> if the integrator board is the only one that cares about this header, then
> it's probably best to keep it in the board-specific dir rather than include/

Yes why not. I'll move it to the board dir, it indeed seems to be a board
pecularity.

Thanks,
Linus Walleij
diff mbox

Patch

diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index 780218c..44e69f1 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -35,6 +35,7 @@ 
 
 #include <common.h>
 #include <netdev.h>
+#include <arm-ebi.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -56,6 +57,8 @@  void show_boot_progress(int progress)
 
 int board_init (void)
 {
+	u32 val;
+
 	/* arch number of Integrator Board */
 #ifdef CONFIG_ARCH_CINTEGRATOR
 	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
@@ -73,6 +76,18 @@  extern void cm_remap(void);
 	cm_remap();	/* remaps writeable memory to 0x00000000 */
 #endif
 
+	/*
+	 * The system comes up with the flash memory non-writable and
+	 * configuration locked. If we want U-Boot to be used for flash
+	 * access we cannot have the flash memory locked.
+	 */
+	writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
+	val = readl(EBI_BASE + EBI_CSR1_REG);
+	val &= EBI_CSR_WREN_MASK;
+	val |= EBI_CSR_WREN_ENABLE;
+	writel(val, EBI_BASE + EBI_CSR1_REG);
+	writel(0, EBI_BASE + EBI_LOCK_REG);
+
 	icache_enable ();
 
 	return 0;
diff --git a/include/arm-ebi.h b/include/arm-ebi.h
new file mode 100644
index 0000000..2d85e3f
--- /dev/null
+++ b/include/arm-ebi.h
@@ -0,0 +1,62 @@ 
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the External Bus Interface (EBI)
+ * found in the ARM Integrator AP and CP reference designs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARM_EBI_H
+#define __ARM_EBI_H
+
+#define EBI_BASE		0x12000000
+
+#define EBI_CSR0_REG		0x00 /* CS0 = Boot ROM */
+#define EBI_CSR1_REG		0x04 /* CS1 = Flash */
+#define EBI_CSR2_REG		0x08 /* CS2 = SSRAM */
+#define EBI_CSR3_REG		0x0C /* CS3 = Expansion memory */
+/*
+ * The four upper bits are the waitstates for each chip select
+ * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
+ */
+#define EBI_CSR_WAIT_MASK	0xF0
+/* Whether memory is synchronous or asynchronous */
+#define EBI_CSR_SYNC_MASK	0xF7
+#define EBI_CSR_ASYNC		0x00
+#define EBI_CSR_SYNC		0x08
+/* Whether memory is write enabled or not */
+#define EBI_CSR_WREN_MASK	0xFB
+#define EBI_CSR_WREN_DISABLE	0x00
+#define EBI_CSR_WREN_ENABLE	0x04
+/* Memory bit width for each chip select */
+#define EBI_CSR_MEMSIZE_MASK	0xFC
+#define EBI_CSR_MEMSIZE_8BIT	0x00
+#define EBI_CSR_MEMSIZE_16BIT	0x01
+#define EBI_CSR_MEMSIZE_32BIT	0x02
+
+/*
+ * The lock register need to be written with 0xa05f before anything in the
+ * EBI can be changed.
+ */
+#define EBI_LOCK_REG		0x20
+#define EBI_UNLOCK_MAGIC	0xA05F
+
+#endif