From patchwork Sun Sep 18 07:52:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 115221 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B9D95B70C0 for ; Sun, 18 Sep 2011 17:53:30 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5B875282F3; Sun, 18 Sep 2011 09:53:29 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Qf58CBUPZ4dK; Sun, 18 Sep 2011 09:53:28 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 970BA282E5; Sun, 18 Sep 2011 09:53:26 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 617EA282E5 for ; Sun, 18 Sep 2011 09:53:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qH+e-TJUmjIC for ; Sun, 18 Sep 2011 09:53:09 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.df.lth.se (mail.df.lth.se [194.47.250.12]) by theia.denx.de (Postfix) with ESMTPS id B7E9D28303 for ; Sun, 18 Sep 2011 09:53:00 +0200 (CEST) Received: from mer.df.lth.se (mer.df.lth.se [194.47.250.37]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.df.lth.se (Postfix) with ESMTPS id 2549365D99; Sun, 18 Sep 2011 09:53:00 +0200 (CEST) Received: from mer.df.lth.se (triad@localhost.localdomain [127.0.0.1]) by mer.df.lth.se (8.14.3/8.14.3/Debian-9.4) with ESMTP id p8I7qxJr018550; Sun, 18 Sep 2011 09:52:59 +0200 Received: (from triad@localhost) by mer.df.lth.se (8.14.3/8.14.3/Submit) id p8I7qxWG018549; Sun, 18 Sep 2011 09:52:59 +0200 From: Linus Walleij To: u-boot@lists.denx.de, Albert ARIBAUD Date: Sun, 18 Sep 2011 09:52:58 +0200 Message-Id: <1316332378-18521-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.7.2.5 Subject: [U-Boot] [PATCH 5/5 v1] integrator: make flash writeable on boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This reconfigures the EBI (External Bus Interface) on the integrator so that chip select 1, handling the flash memory, is set to writeable. Without this it is not possible for U-Boot to access flash memory and it crashes on startup since CFI won't work properly. Since this is the first time we use the EBI, we create a header file for its registers. Signed-off-by: Linus Walleij --- board/armltd/integrator/integrator.c | 15 ++++++++ include/arm-ebi.h | 62 ++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 0 deletions(-) create mode 100644 include/arm-ebi.h diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 780218c..44e69f1 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -35,6 +35,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -56,6 +57,8 @@ void show_boot_progress(int progress) int board_init (void) { + u32 val; + /* arch number of Integrator Board */ #ifdef CONFIG_ARCH_CINTEGRATOR gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; @@ -73,6 +76,18 @@ extern void cm_remap(void); cm_remap(); /* remaps writeable memory to 0x00000000 */ #endif + /* + * The system comes up with the flash memory non-writable and + * configuration locked. If we want U-Boot to be used for flash + * access we cannot have the flash memory locked. + */ + writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG); + val = readl(EBI_BASE + EBI_CSR1_REG); + val &= EBI_CSR_WREN_MASK; + val |= EBI_CSR_WREN_ENABLE; + writel(val, EBI_BASE + EBI_CSR1_REG); + writel(0, EBI_BASE + EBI_LOCK_REG); + icache_enable (); return 0; diff --git a/include/arm-ebi.h b/include/arm-ebi.h new file mode 100644 index 0000000..2d85e3f --- /dev/null +++ b/include/arm-ebi.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2011 + * Linaro + * Linus Walleij + * Register definitions for the External Bus Interface (EBI) + * found in the ARM Integrator AP and CP reference designs + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARM_EBI_H +#define __ARM_EBI_H + +#define EBI_BASE 0x12000000 + +#define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */ +#define EBI_CSR1_REG 0x04 /* CS1 = Flash */ +#define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */ +#define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */ +/* + * The four upper bits are the waitstates for each chip select + * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles + */ +#define EBI_CSR_WAIT_MASK 0xF0 +/* Whether memory is synchronous or asynchronous */ +#define EBI_CSR_SYNC_MASK 0xF7 +#define EBI_CSR_ASYNC 0x00 +#define EBI_CSR_SYNC 0x08 +/* Whether memory is write enabled or not */ +#define EBI_CSR_WREN_MASK 0xFB +#define EBI_CSR_WREN_DISABLE 0x00 +#define EBI_CSR_WREN_ENABLE 0x04 +/* Memory bit width for each chip select */ +#define EBI_CSR_MEMSIZE_MASK 0xFC +#define EBI_CSR_MEMSIZE_8BIT 0x00 +#define EBI_CSR_MEMSIZE_16BIT 0x01 +#define EBI_CSR_MEMSIZE_32BIT 0x02 + +/* + * The lock register need to be written with 0xa05f before anything in the + * EBI can be changed. + */ +#define EBI_LOCK_REG 0x20 +#define EBI_UNLOCK_MAGIC 0xA05F + +#endif