| Message ID | 20200610113748.4754-58-zhiwei_liu@c-sky.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: support vector extension v0.7.1 | expand |
On Wed, Jun 10, 2020 at 6:44 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Hello, This patch fails to compile with this error: target/riscv/insn32.decode:566: error: undefined format @r2rd Do you mind looking into why this test fails? Alistair > --- > target/riscv/insn32.decode | 2 + > target/riscv/insn_trans/trans_rvv.inc.c | 49 +++++++++++++++++++++++++ > 2 files changed, 51 insertions(+) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 0741a25540..79f9b37b29 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -563,6 +563,8 @@ viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm > vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm > vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r > vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 > +vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd > +vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c > index e67eff0a7f..884ad910b1 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -2709,3 +2709,52 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) > } > return false; > } > + > +/* Floating-Point Scalar Move Instructions */ > +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) > +{ > + if (!s->vill && has_ext(s, RVF) && > + (s->mstatus_fs != 0) && (s->sew != 0)) { > + unsigned int len = 8 << s->sew; > + > + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); > + if (len < 64) { > + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], > + MAKE_64BIT_MASK(len, 64 - len)); > + } > + > + mark_fs_dirty(s); > + return true; > + } > + return false; > +} > + > +/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ > +static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) > +{ > + if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { > + TCGv_i64 t1; > + /* The instructions ignore LMUL and vector register group. */ > + uint32_t vlmax = s->vlen >> 3; > + > + /* if vl == 0, skip vector register write back */ > + TCGLabel *over = gen_new_label(); > + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); > + > + /* zeroed all elements */ > + tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); > + > + /* NaN-box f[rs1] as necessary for SEW */ > + t1 = tcg_temp_new_i64(); > + if (s->sew == MO_64 && !has_ext(s, RVD)) { > + tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); > + } else { > + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); > + } > + vec_element_storei(s, a->rd, 0, t1); > + tcg_temp_free_i64(t1); > + gen_set_label(over); > + return true; > + } > + return false; > +} > -- > 2.23.0 > >
On Fri, Jun 19, 2020 at 6:09 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > > > On 2020/6/20 8:44, Alistair Francis wrote: > > On Wed, Jun 10, 2020 at 6:44 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > >> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > Hello, > > > > This patch fails to compile with this error: > > > > target/riscv/insn32.decode:566: error: undefined format @r2rd > > > > Do you mind looking into why this test fails? > Sorry, it's a mistake. > > the @r2rd is defined in the next patch "[PATCH v9 58/61] target/riscv: > vector slide instructions", where doesn't need the definition at all. > > When I split patch set, I must make a mistake here. After that I only > build and tested the whole patch set. > > Thanks for pointing it. No worries. Do you mind fixing that problem and also rebasing the series on this branch (it should be in master in a few days): https://github.com/alistair23/qemu/tree/riscv-to-apply.next Then send a new patch series. Alistair > > Zhiwei > > > > Alistair > > > > > >> --- > >> target/riscv/insn32.decode | 2 + > >> target/riscv/insn_trans/trans_rvv.inc.c | 49 +++++++++++++++++++++++++ > >> 2 files changed, 51 insertions(+) > >> > >> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > >> index 0741a25540..79f9b37b29 100644 > >> --- a/target/riscv/insn32.decode > >> +++ b/target/riscv/insn32.decode > >> @@ -563,6 +563,8 @@ viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm > >> vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm > >> vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r > >> vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 > >> +vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd > >> +vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 > >> > >> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > >> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > >> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c > >> index e67eff0a7f..884ad910b1 100644 > >> --- a/target/riscv/insn_trans/trans_rvv.inc.c > >> +++ b/target/riscv/insn_trans/trans_rvv.inc.c > >> @@ -2709,3 +2709,52 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) > >> } > >> return false; > >> } > >> + > >> +/* Floating-Point Scalar Move Instructions */ > >> +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) > >> +{ > >> + if (!s->vill && has_ext(s, RVF) && > >> + (s->mstatus_fs != 0) && (s->sew != 0)) { > >> + unsigned int len = 8 << s->sew; > >> + > >> + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); > >> + if (len < 64) { > >> + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], > >> + MAKE_64BIT_MASK(len, 64 - len)); > >> + } > >> + > >> + mark_fs_dirty(s); > >> + return true; > >> + } > >> + return false; > >> +} > >> + > >> +/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ > >> +static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) > >> +{ > >> + if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { > >> + TCGv_i64 t1; > >> + /* The instructions ignore LMUL and vector register group. */ > >> + uint32_t vlmax = s->vlen >> 3; > >> + > >> + /* if vl == 0, skip vector register write back */ > >> + TCGLabel *over = gen_new_label(); > >> + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); > >> + > >> + /* zeroed all elements */ > >> + tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); > >> + > >> + /* NaN-box f[rs1] as necessary for SEW */ > >> + t1 = tcg_temp_new_i64(); > >> + if (s->sew == MO_64 && !has_ext(s, RVD)) { > >> + tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); > >> + } else { > >> + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); > >> + } > >> + vec_element_storei(s, a->rd, 0, t1); > >> + tcg_temp_free_i64(t1); > >> + gen_set_label(over); > >> + return true; > >> + } > >> + return false; > >> +} > >> -- > >> 2.23.0 > >> > >> >
On 2020/6/20 8:44, Alistair Francis wrote: > On Wed, Jun 10, 2020 at 6:44 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: >> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Hello, > > This patch fails to compile with this error: > > target/riscv/insn32.decode:566: error: undefined format @r2rd > > Do you mind looking into why this test fails? Sorry, it's a mistake. the @r2rd is defined in the next patch "[PATCH v9 58/61] target/riscv: vector slide instructions", where doesn't need the definition at all. When I split patch set, I must make a mistake here. After that I only build and tested the whole patch set. Thanks for pointing it. Zhiwei > > Alistair > > >> --- >> target/riscv/insn32.decode | 2 + >> target/riscv/insn_trans/trans_rvv.inc.c | 49 +++++++++++++++++++++++++ >> 2 files changed, 51 insertions(+) >> >> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode >> index 0741a25540..79f9b37b29 100644 >> --- a/target/riscv/insn32.decode >> +++ b/target/riscv/insn32.decode >> @@ -563,6 +563,8 @@ viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm >> vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm >> vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r >> vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 >> +vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd >> +vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 >> >> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm >> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r >> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c >> index e67eff0a7f..884ad910b1 100644 >> --- a/target/riscv/insn_trans/trans_rvv.inc.c >> +++ b/target/riscv/insn_trans/trans_rvv.inc.c >> @@ -2709,3 +2709,52 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) >> } >> return false; >> } >> + >> +/* Floating-Point Scalar Move Instructions */ >> +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) >> +{ >> + if (!s->vill && has_ext(s, RVF) && >> + (s->mstatus_fs != 0) && (s->sew != 0)) { >> + unsigned int len = 8 << s->sew; >> + >> + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); >> + if (len < 64) { >> + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], >> + MAKE_64BIT_MASK(len, 64 - len)); >> + } >> + >> + mark_fs_dirty(s); >> + return true; >> + } >> + return false; >> +} >> + >> +/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ >> +static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) >> +{ >> + if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { >> + TCGv_i64 t1; >> + /* The instructions ignore LMUL and vector register group. */ >> + uint32_t vlmax = s->vlen >> 3; >> + >> + /* if vl == 0, skip vector register write back */ >> + TCGLabel *over = gen_new_label(); >> + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); >> + >> + /* zeroed all elements */ >> + tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); >> + >> + /* NaN-box f[rs1] as necessary for SEW */ >> + t1 = tcg_temp_new_i64(); >> + if (s->sew == MO_64 && !has_ext(s, RVD)) { >> + tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); >> + } else { >> + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); >> + } >> + vec_element_storei(s, a->rd, 0, t1); >> + tcg_temp_free_i64(t1); >> + gen_set_label(over); >> + return true; >> + } >> + return false; >> +} >> -- >> 2.23.0 >> >>
On 2020/6/20 9:06, Alistair Francis wrote: > On Fri, Jun 19, 2020 at 6:09 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: >> >> >> On 2020/6/20 8:44, Alistair Francis wrote: >>> On Wed, Jun 10, 2020 at 6:44 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: >>>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> >>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >>> Hello, >>> >>> This patch fails to compile with this error: >>> >>> target/riscv/insn32.decode:566: error: undefined format @r2rd >>> >>> Do you mind looking into why this test fails? >> Sorry, it's a mistake. >> >> the @r2rd is defined in the next patch "[PATCH v9 58/61] target/riscv: >> vector slide instructions", where doesn't need the definition at all. >> >> When I split patch set, I must make a mistake here. After that I only >> build and tested the whole patch set. >> >> Thanks for pointing it. > No worries. > > Do you mind fixing that problem and also rebasing the series on this > branch (it should be in master in a few days): > https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > Then send a new patch series. Of course not. I will rebase and send it later. Zhiwei > > Alistair > >> Zhiwei >>> Alistair >>> >>> >>>> --- >>>> target/riscv/insn32.decode | 2 + >>>> target/riscv/insn_trans/trans_rvv.inc.c | 49 +++++++++++++++++++++++++ >>>> 2 files changed, 51 insertions(+) >>>> >>>> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode >>>> index 0741a25540..79f9b37b29 100644 >>>> --- a/target/riscv/insn32.decode >>>> +++ b/target/riscv/insn32.decode >>>> @@ -563,6 +563,8 @@ viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm >>>> vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm >>>> vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r >>>> vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 >>>> +vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd >>>> +vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 >>>> >>>> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm >>>> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r >>>> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c >>>> index e67eff0a7f..884ad910b1 100644 >>>> --- a/target/riscv/insn_trans/trans_rvv.inc.c >>>> +++ b/target/riscv/insn_trans/trans_rvv.inc.c >>>> @@ -2709,3 +2709,52 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) >>>> } >>>> return false; >>>> } >>>> + >>>> +/* Floating-Point Scalar Move Instructions */ >>>> +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) >>>> +{ >>>> + if (!s->vill && has_ext(s, RVF) && >>>> + (s->mstatus_fs != 0) && (s->sew != 0)) { >>>> + unsigned int len = 8 << s->sew; >>>> + >>>> + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); >>>> + if (len < 64) { >>>> + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], >>>> + MAKE_64BIT_MASK(len, 64 - len)); >>>> + } >>>> + >>>> + mark_fs_dirty(s); >>>> + return true; >>>> + } >>>> + return false; >>>> +} >>>> + >>>> +/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ >>>> +static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) >>>> +{ >>>> + if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { >>>> + TCGv_i64 t1; >>>> + /* The instructions ignore LMUL and vector register group. */ >>>> + uint32_t vlmax = s->vlen >> 3; >>>> + >>>> + /* if vl == 0, skip vector register write back */ >>>> + TCGLabel *over = gen_new_label(); >>>> + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); >>>> + >>>> + /* zeroed all elements */ >>>> + tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); >>>> + >>>> + /* NaN-box f[rs1] as necessary for SEW */ >>>> + t1 = tcg_temp_new_i64(); >>>> + if (s->sew == MO_64 && !has_ext(s, RVD)) { >>>> + tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); >>>> + } else { >>>> + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); >>>> + } >>>> + vec_element_storei(s, a->rd, 0, t1); >>>> + tcg_temp_free_i64(t1); >>>> + gen_set_label(over); >>>> + return true; >>>> + } >>>> + return false; >>>> +} >>>> -- >>>> 2.23.0 >>>> >>>>
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0741a25540..79f9b37b29 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -563,6 +563,8 @@ viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 +vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd +vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index e67eff0a7f..884ad910b1 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2709,3 +2709,52 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) } return false; } + +/* Floating-Point Scalar Move Instructions */ +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) +{ + if (!s->vill && has_ext(s, RVF) && + (s->mstatus_fs != 0) && (s->sew != 0)) { + unsigned int len = 8 << s->sew; + + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); + if (len < 64) { + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], + MAKE_64BIT_MASK(len, 64 - len)); + } + + mark_fs_dirty(s); + return true; + } + return false; +} + +/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ +static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) +{ + if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { + TCGv_i64 t1; + /* The instructions ignore LMUL and vector register group. */ + uint32_t vlmax = s->vlen >> 3; + + /* if vl == 0, skip vector register write back */ + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + /* zeroed all elements */ + tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); + + /* NaN-box f[rs1] as necessary for SEW */ + t1 = tcg_temp_new_i64(); + if (s->sew == MO_64 && !has_ext(s, RVD)) { + tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); + } else { + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + } + vec_element_storei(s, a->rd, 0, t1); + tcg_temp_free_i64(t1); + gen_set_label(over); + return true; + } + return false; +}