[v9,00/61] target/riscv: support vector extension v0.7.1

This patchset implements the vector extension for RISC-V on QEMU.

You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v9).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode programs.

You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh.

Features:
  * support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/)
  * support basic vector extension.
  * support Zvlsseg.
  * support Zvamo.
  * not support Zvediv as it is changing.
  * SLEN always equals VLEN.
  * element width support 8bit, 16bit, 32bit, 64bit.

Changelog:
v9
  * always set dynamic rounding mode for vector float insns.
  * bug fix atomic implementation.
  * bug fix first-only-fault.
  * some small tidy up.

v8
  * support different float rounding modes for vector instructions.
  * use lastest released TCG GVEC DUP IR.
  * set RV_VLEN_MAX to 256 bits, as GVEC IR uses simd_desc.

v7
  * move vl == 0 check to translation time by add a global cpu_vl.
  * implement vector element inline load and store function by TCG IR.
  * based on vec_element_load(store), implement some permutation instructions.
  * implement rsubs GVEC IR.
  * fixup vsmul, vmfne, vfmerge, vslidedown.
  * some other small bugs and indentation errors.

v6
  * use gvec_dup Gvec IR to accellerate move and merge.
  * a better way to implement fixed point instructions.
  * a global check when vl == 0.
  * limit some macros to only one inline function call.
  * fixup sew error when use Gvec IR.
  * fixup bugs for corner cases.

v5
  * fixup a bug in tb flags.

v4
  * no change

v3
  * move check code from execution-time to translation-time
  * use a continous memory block for vector register description.
  * vector registers as direct fields in RISCVCPUState.
  * support VLEN configure from qemu command line.
  * support ELEN configure from qemu command line.
  * support vector specification version configure from qemu command line.
  * probe pages before real load or store access.
  * use probe_page_check for no-fault operations in linux user mode.
  * generation atomic exit exception when in parallel environment.
  * fixup a lot of concrete bugs.

V2
  * use float16_compare{_quiet}
  * only use GETPC() in outer most helper
  * add ctx.ext_v Property

LIU Zhiwei (61):
  target/riscv: add vector extension field in CPURISCVState
  target/riscv: implementation-defined constant parameters
  target/riscv: support vector extension csr
  target/riscv: add vector configure instruction
  target/riscv: add an internals.h header
  target/riscv: add vector stride load and store instructions
  target/riscv: add vector index load and store instructions
  target/riscv: add fault-only-first unit stride load
  target/riscv: add vector amo operations
  target/riscv: vector single-width integer add and subtract
  target/riscv: vector widening integer add and subtract
  target/riscv: vector integer add-with-carry / subtract-with-borrow
    instructions
  target/riscv: vector bitwise logical instructions
  target/riscv: vector single-width bit shift instructions
  target/riscv: vector narrowing integer right shift instructions
  target/riscv: vector integer comparison instructions
  target/riscv: vector integer min/max instructions
  target/riscv: vector single-width integer multiply instructions
  target/riscv: vector integer divide instructions
  target/riscv: vector widening integer multiply instructions
  target/riscv: vector single-width integer multiply-add instructions
  target/riscv: vector widening integer multiply-add instructions
  target/riscv: vector integer merge and move instructions
  target/riscv: vector single-width saturating add and subtract
  target/riscv: vector single-width averaging add and subtract
  target/riscv: vector single-width fractional multiply with rounding
    and saturation
  target/riscv: vector widening saturating scaled multiply-add
  target/riscv: vector single-width scaling shift instructions
  target/riscv: vector narrowing fixed-point clip instructions
  target/riscv: vector single-width floating-point add/subtract
    instructions
  target/riscv: vector widening floating-point add/subtract instructions
  target/riscv: vector single-width floating-point multiply/divide
    instructions
  target/riscv: vector widening floating-point multiply
  target/riscv: vector single-width floating-point fused multiply-add
    instructions
  target/riscv: vector widening floating-point fused multiply-add
    instructions
  target/riscv: vector floating-point square-root instruction
  target/riscv: vector floating-point min/max instructions
  target/riscv: vector floating-point sign-injection instructions
  target/riscv: vector floating-point compare instructions
  target/riscv: vector floating-point classify instructions
  target/riscv: vector floating-point merge instructions
  target/riscv: vector floating-point/integer type-convert instructions
  target/riscv: widening floating-point/integer type-convert
    instructions
  target/riscv: narrowing floating-point/integer type-convert
    instructions
  target/riscv: vector single-width integer reduction instructions
  target/riscv: vector wideing integer reduction instructions
  target/riscv: vector single-width floating-point reduction
    instructions
  target/riscv: vector widening floating-point reduction instructions
  target/riscv: vector mask-register logical instructions
  target/riscv: vector mask population count vmpopc
  target/riscv: vmfirst find-first-set mask bit
  target/riscv: set-X-first mask bit
  target/riscv: vector iota instruction
  target/riscv: vector element index instruction
  target/riscv: integer extract instruction
  target/riscv: integer scalar move instruction
  target/riscv: floating-point scalar move instructions
  target/riscv: vector slide instructions
  target/riscv: vector register gather instruction
  target/riscv: vector compress instruction
  target/riscv: configure and turn on vector extension from command line

 target/riscv/Makefile.objs              |    2 +-
 target/riscv/cpu.c                      |   50 +
 target/riscv/cpu.h                      |   82 +-
 target/riscv/cpu_bits.h                 |   15 +
 target/riscv/csr.c                      |   75 +-
 target/riscv/fpu_helper.c               |   33 +-
 target/riscv/helper.h                   | 1068 +++++
 target/riscv/insn32-64.decode           |   11 +
 target/riscv/insn32.decode              |  372 ++
 target/riscv/insn_trans/trans_rvv.inc.c | 2888 +++++++++++++
 target/riscv/internals.h                |   41 +
 target/riscv/translate.c                |   27 +-
 target/riscv/vector_helper.c            | 4899 +++++++++++++++++++++++
 13 files changed, 9519 insertions(+), 44 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
 create mode 100644 target/riscv/internals.h
 create mode 100644 target/riscv/vector_helper.c

Patchew URL: https://patchew.org/QEMU/20200610113748.4754-1-zhiwei_liu@c-sky.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20200610113748.4754-1-zhiwei_liu@c-sky.com
Subject: [PATCH v9 00/61] target/riscv: support vector extension v0.7.1
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Switched to a new branch 'test'
009eb3c target/riscv: configure and turn on vector extension from command line
c18ff83 target/riscv: vector compress instruction
759ba48 target/riscv: vector register gather instruction
1817571 target/riscv: vector slide instructions
05fc96d target/riscv: floating-point scalar move instructions
6d587fd target/riscv: integer scalar move instruction
b0b3995 target/riscv: integer extract instruction
fc23143 target/riscv: vector element index instruction
d36d921 target/riscv: vector iota instruction
67bdc7d target/riscv: set-X-first mask bit
e657761 target/riscv: vmfirst find-first-set mask bit
1113748 target/riscv: vector mask population count vmpopc
b94ef00 target/riscv: vector mask-register logical instructions
71bfecf target/riscv: vector widening floating-point reduction instructions
bb02d58 target/riscv: vector single-width floating-point reduction instructions
6d69161 target/riscv: vector wideing integer reduction instructions
3035675 target/riscv: vector single-width integer reduction instructions
ca6f896 target/riscv: narrowing floating-point/integer type-convert instructions
6f234ed target/riscv: widening floating-point/integer type-convert instructions
7d1cbc1 target/riscv: vector floating-point/integer type-convert instructions
7849fdd target/riscv: vector floating-point merge instructions
a0235e7 target/riscv: vector floating-point classify instructions
befb061 target/riscv: vector floating-point compare instructions
1d89511 target/riscv: vector floating-point sign-injection instructions
d48a061 target/riscv: vector floating-point min/max instructions
e2769bc target/riscv: vector floating-point square-root instruction
27e2cab target/riscv: vector widening floating-point fused multiply-add instructions
1152fc4 target/riscv: vector single-width floating-point fused multiply-add instructions
d94c8c9 target/riscv: vector widening floating-point multiply
e474319 target/riscv: vector single-width floating-point multiply/divide instructions
e13937e target/riscv: vector widening floating-point add/subtract instructions
3ae567b target/riscv: vector single-width floating-point add/subtract instructions
9f482f9 target/riscv: vector narrowing fixed-point clip instructions
fd341c2 target/riscv: vector single-width scaling shift instructions
770e39b target/riscv: vector widening saturating scaled multiply-add
f6bc55a target/riscv: vector single-width fractional multiply with rounding and saturation
f9b9fcb target/riscv: vector single-width averaging add and subtract
71f901d target/riscv: vector single-width saturating add and subtract
4ae98b5 target/riscv: vector integer merge and move instructions
776567d target/riscv: vector widening integer multiply-add instructions
4880500 target/riscv: vector single-width integer multiply-add instructions
e9b095a target/riscv: vector widening integer multiply instructions
c9f9f8e target/riscv: vector integer divide instructions
ed8b7d0 target/riscv: vector single-width integer multiply instructions
ac3a251 target/riscv: vector integer min/max instructions
02ca606 target/riscv: vector integer comparison instructions
c140049 target/riscv: vector narrowing integer right shift instructions
6f3dfb6 target/riscv: vector single-width bit shift instructions
bf27418 target/riscv: vector bitwise logical instructions
3cb66f5 target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
02909e2 target/riscv: vector widening integer add and subtract
8b3781b target/riscv: vector single-width integer add and subtract
c3d3bb8 target/riscv: add vector amo operations
ac6f86e target/riscv: add fault-only-first unit stride load
ea3199e target/riscv: add vector index load and store instructions
bb0f822 target/riscv: add vector stride load and store instructions
cb32983 target/riscv: add an internals.h header
3093e4e target/riscv: add vector configure instruction
bcdeea4 target/riscv: support vector extension csr
0aa664c target/riscv: implementation-defined constant parameters
c852671 target/riscv: add vector extension field in CPURISCVState

=== OUTPUT BEGIN ===
1/61 Checking commit c852671c36fd (target/riscv: add vector extension field in CPURISCVState)
2/61 Checking commit 0aa664c1c8a5 (target/riscv: implementation-defined constant parameters)
3/61 Checking commit bcdeea452ae1 (target/riscv: support vector extension csr)
4/61 Checking commit 3093e4e40d37 (target/riscv: add vector configure instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#160: 
new file mode 100644

total: 0 errors, 1 warnings, 294 lines checked

Patch 4/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/61 Checking commit cb329836a65a (target/riscv: add an internals.h header)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16: 
new file mode 100644

total: 0 errors, 1 warnings, 24 lines checked

Patch 5/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/61 Checking commit bb0f822abb05 (target/riscv: add vector stride load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#274: FILE: target/riscv/insn_trans/trans_rvv.inc.c:143:
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                    ^

ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+                 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                         ^

ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+             vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
                                                     ^

total: 5 errors, 0 warnings, 982 lines checked

Patch 6/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

7/61 Checking commit ea3199e9f9db (target/riscv: add vector index load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#251: FILE: target/riscv/vector_helper.c:487:
+                vext_ldst_elem_fn *ldst_elem,
                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#252: FILE: target/riscv/vector_helper.c:488:
+                clear_fn *clear_elem,
                          ^

total: 2 errors, 0 warnings, 308 lines checked

Patch 7/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

8/61 Checking commit ac6f86e2774f (target/riscv: add fault-only-first unit stride load)
ERROR: spaces required around that '*' (ctx:WxV)
#161: FILE: target/riscv/vector_helper.c:587:
+          vext_ldst_elem_fn *ldst_elem,
                             ^

ERROR: spaces required around that '*' (ctx:WxV)
#162: FILE: target/riscv/vector_helper.c:588:
+          clear_fn *clear_elem,
                    ^

total: 2 errors, 0 warnings, 227 lines checked

Patch 8/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

9/61 Checking commit c3d3bb8c0f33 (target/riscv: add vector amo operations)
ERROR: spaces required around that '*' (ctx:WxV)
#365: FILE: target/riscv/vector_helper.c:770:
+                  vext_amo_noatomic_fn *noatomic_op,
                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#366: FILE: target/riscv/vector_helper.c:771:
+                  clear_fn *clear_elem,
                            ^

total: 2 errors, 0 warnings, 382 lines checked

Patch 9/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

10/61 Checking commit 8b3781be42d8 (target/riscv: vector single-width integer add and subtract)
ERROR: spaces required around that '*' (ctx:WxV)
#93: FILE: target/riscv/insn_trans/trans_rvv.inc.c:781:
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
                                                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:876:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                  ^

ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:876:
+                       opivv2_fn *fn, clear_fn *clearfn)
                                                ^

ERROR: spaces required around that '*' (ctx:WxV)
#490: FILE: target/riscv/vector_helper.c:941:
+                       opivx2_fn fn, clear_fn *clearfn)
                                               ^

total: 4 errors, 0 warnings, 535 lines checked

Patch 10/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/61 Checking commit 02909e204869 (target/riscv: vector widening integer add and subtract)
12/61 Checking commit 3cb66f569dc2 (target/riscv: vector integer add-with-carry / subtract-with-borrow instructions)
13/61 Checking commit bf27418041a2 (target/riscv: vector bitwise logical instructions)
14/61 Checking commit 6f3dfb6357e2 (target/riscv: vector single-width bit shift instructions)
15/61 Checking commit c1400496773e (target/riscv: vector narrowing integer right shift instructions)
16/61 Checking commit 02ca606737a2 (target/riscv: vector integer comparison instructions)
17/61 Checking commit ac3a251a17ba (target/riscv: vector integer min/max instructions)
18/61 Checking commit ed8b7d0986d4 (target/riscv: vector single-width integer multiply instructions)
19/61 Checking commit c9f9f8eb27ae (target/riscv: vector integer divide instructions)
20/61 Checking commit e9b095aa0042 (target/riscv: vector widening integer multiply instructions)
21/61 Checking commit 488050078a6a (target/riscv: vector single-width integer multiply-add instructions)
22/61 Checking commit 776567d8b9eb (target/riscv: vector widening integer multiply-add instructions)
23/61 Checking commit 4ae98b54134b (target/riscv: vector integer merge and move instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#72: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1623:
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
                                                        ^

total: 1 errors, 0 warnings, 246 lines checked

Patch 23/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

24/61 Checking commit 71f901d0f90f (target/riscv: vector single-width saturating add and subtract)
25/61 Checking commit f9b9fcb64084 (target/riscv: vector single-width averaging add and subtract)
26/61 Checking commit f6bc55a7b8be (target/riscv: vector single-width fractional multiply with rounding and saturation)
27/61 Checking commit 770e39b2da1a (target/riscv: vector widening saturating scaled multiply-add)
28/61 Checking commit fd341c2d47dc (target/riscv: vector single-width scaling shift instructions)
29/61 Checking commit 9f482f9b6621 (target/riscv: vector narrowing fixed-point clip instructions)
30/61 Checking commit 3ae567bcab6b (target/riscv: vector single-width floating-point add/subtract instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#283: FILE: target/riscv/vector_helper.c:3260:
+static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
                                                                   ^

total: 1 errors, 0 warnings, 271 lines checked

Patch 30/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

31/61 Checking commit e13937e8606d (target/riscv: vector widening floating-point add/subtract instructions)
32/61 Checking commit e474319edcbd (target/riscv: vector single-width floating-point multiply/divide instructions)
33/61 Checking commit d94c8c9d7210 (target/riscv: vector widening floating-point multiply)
34/61 Checking commit 1152fc4ed15f (target/riscv: vector single-width floating-point fused multiply-add instructions)
35/61 Checking commit 27e2caba95c8 (target/riscv: vector widening floating-point fused multiply-add instructions)
36/61 Checking commit e2769bc0fa04 (target/riscv: vector floating-point square-root instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#67: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2099:
+static bool opfv_check(DisasContext *s, arg_rmr *a)
                                                 ^

ERROR: spaces required around that '*' (ctx:WxV)
#77: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2109:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 120 lines checked

Patch 36/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

37/61 Checking commit d48a061e1221 (target/riscv: vector floating-point min/max instructions)
38/61 Checking commit 1d89511bce7b (target/riscv: vector floating-point sign-injection instructions)
39/61 Checking commit befb0614631b (target/riscv: vector floating-point compare instructions)
40/61 Checking commit a0235e711a15 (target/riscv: vector floating-point classify instructions)
41/61 Checking commit 7849fdd18a93 (target/riscv: vector floating-point merge instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#49: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2191:
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
                                                          ^

total: 1 errors, 0 warnings, 83 lines checked

Patch 41/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

42/61 Checking commit 7d1cbc1fffe5 (target/riscv: vector floating-point/integer type-convert instructions)
43/61 Checking commit 6f234edd7d18 (target/riscv: widening floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2238:
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
                                                       ^

ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2250:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 121 lines checked

Patch 43/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

44/61 Checking commit ca6f89659b55 (target/riscv: narrowing floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2286:
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
                                                        ^

ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2298:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
                                                   ^

total: 2 errors, 0 warnings, 118 lines checked

Patch 44/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

45/61 Checking commit 3035675ac48d (target/riscv: vector single-width integer reduction instructions)
46/61 Checking commit 6d691616355c (target/riscv: vector wideing integer reduction instructions)
47/61 Checking commit bb02d58514bf (target/riscv: vector single-width floating-point reduction instructions)
48/61 Checking commit 71bfecf3b4a7 (target/riscv: vector widening floating-point reduction instructions)
49/61 Checking commit b94ef00bd964 (target/riscv: vector mask-register logical instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2364:
+static bool trans_##NAME(DisasContext *s, arg_r *a)                \
                                                 ^

total: 1 errors, 0 warnings, 107 lines checked

Patch 49/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

50/61 Checking commit 1113748cc13f (target/riscv: vector mask population count vmpopc)
ERROR: spaces required around that '*' (ctx:WxV)
#43: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2394:
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
                                                     ^

total: 1 errors, 0 warnings, 70 lines checked

Patch 50/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

51/61 Checking commit e6577614af31 (target/riscv: vmfirst find-first-set mask bit)
52/61 Checking commit 67bdc7d67809 (target/riscv: set-X-first mask bit)
53/61 Checking commit d36d92141124 (target/riscv: vector iota instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#46: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2486:
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
                                                        ^

total: 1 errors, 0 warnings, 77 lines checked

Patch 53/61 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

54/61 Checking commit fc23143cb92f (target/riscv: vector element index instruction)
55/61 Checking commit b0b399526d8a (target/riscv: integer extract instruction)
56/61 Checking commit 6d587fd0b899 (target/riscv: integer scalar move instruction)
57/61 Checking commit 05fc96dfb901 (target/riscv: floating-point scalar move instructions)
58/61 Checking commit 1817571f415a (target/riscv: vector slide instructions)
59/61 Checking commit 759ba48e9c23 (target/riscv: vector register gather instruction)
60/61 Checking commit c18ff8324815 (target/riscv: vector compress instruction)
61/61 Checking commit 009eb3c6d157 (target/riscv: configure and turn on vector extension from command line)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200610113748.4754-1-zhiwei_liu@c-sky.com/testing.checkpatch/?type=message.
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