| Message ID | 1497619909-29454-20-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Bin Meng |
| Headers | show |
On 16 June 2017 at 07:31, Bin Meng <bmeng.cn@gmail.com> wrote: > BayTrail SoC supports both EHCI and xHCI controllers. However only > one host controller (either EHCI or xHCI) can be used. To enable > HSIC and SS ports, xHCI must be used. This turns on xHCI support on > Intel MinnowMax board. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > arch/x86/dts/minnowmax.dts | 3 +++ > configs/minnowmax_defconfig | 1 + > 2 files changed, 4 insertions(+) Reviewed-by: Simon Glass <sjg@chromium.org> Arguably there is no point in the #ifdef in the .dts file, since this file should be in sync with the defconfig. > > diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts > index 4c0a8fe..a0ad03c 100644 > --- a/arch/x86/dts/minnowmax.dts > +++ b/arch/x86/dts/minnowmax.dts > @@ -272,6 +272,9 @@ > fsp,enable-spi; > fsp,enable-sata; > fsp,sata-mode = <SATA_MODE_AHCI>; > +#ifdef CONFIG_USB_XHCI_HCD > + fsp,enable-xhci; > +#endif > fsp,lpe-mode = <LPE_MODE_PCI>; > fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; > fsp,enable-dma0; > diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig > index aa50e88..289b4c8 100644 > --- a/configs/minnowmax_defconfig > +++ b/configs/minnowmax_defconfig > @@ -68,6 +68,7 @@ CONFIG_ICH_SPI=y > CONFIG_TIMER=y > CONFIG_USB=y > CONFIG_DM_USB=y > +CONFIG_USB_XHCI_HCD=y > CONFIG_USB_STORAGE=y > CONFIG_USB_KEYBOARD=y > CONFIG_DM_VIDEO=y > -- > 2.9.2 >
Hi Simon, On Sat, Jun 17, 2017 at 11:44 AM, Simon Glass <sjg@chromium.org> wrote: > On 16 June 2017 at 07:31, Bin Meng <bmeng.cn@gmail.com> wrote: >> BayTrail SoC supports both EHCI and xHCI controllers. However only >> one host controller (either EHCI or xHCI) can be used. To enable >> HSIC and SS ports, xHCI must be used. This turns on xHCI support on >> Intel MinnowMax board. >> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >> --- >> >> arch/x86/dts/minnowmax.dts | 3 +++ >> configs/minnowmax_defconfig | 1 + >> 2 files changed, 4 insertions(+) > > Reviewed-by: Simon Glass <sjg@chromium.org> > > Arguably there is no point in the #ifdef in the .dts file, since this > file should be in sync with the defconfig. > Yep, but I wanted to do 'make minnowmax_defconfig', 'make menuconfig' to remove CONFIG_USB_XHCI_HCD and 'make'. This way I can get an EHCI enabled U-Boot without manually editing the device tree. Regards, Bin
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 4c0a8fe..a0ad03c 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -272,6 +272,9 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = <SATA_MODE_AHCI>; +#ifdef CONFIG_USB_XHCI_HCD + fsp,enable-xhci; +#endif fsp,lpe-mode = <LPE_MODE_PCI>; fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; fsp,enable-dma0; diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index aa50e88..289b4c8 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -68,6 +68,7 @@ CONFIG_ICH_SPI=y CONFIG_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y
BayTrail SoC supports both EHCI and xHCI controllers. However only one host controller (either EHCI or xHCI) can be used. To enable HSIC and SS ports, xHCI must be used. This turns on xHCI support on Intel MinnowMax board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/dts/minnowmax.dts | 3 +++ configs/minnowmax_defconfig | 1 + 2 files changed, 4 insertions(+)