diff mbox

[U-Boot,21/21] arm: imx: add i.MX6ULL 14x14 EVK board support

Message ID 1470895377-2502-22-git-send-email-peng.fan@nxp.com
State Accepted
Commit 55a42b33f2e9b9f6330396fc6d89878a5deacc75
Delegated to: Stefano Babic
Headers show

Commit Message

Peng Fan Aug. 11, 2016, 6:02 a.m. UTC 
Add i.MX6ULL EVK board support:
Add device tree file, which is copied from NXP Linux.
Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
The uart iomux settings are still keeped in board file.

Boot Log:
U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)

CPU:   Freescale i.MX6ULL rev1.0 at 396MHz
CPU:   Commercial temperature grade (0C to 95C) at 15C
Reset cause: POR
Model: Freescale i.MX6 ULL 14x14 EVK Board
Board: MX6ULL 14x14 EVK
DRAM:  512 MiB
MMC:   initialized IMX pinctrl driver
FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/armv7/mx6/Kconfig         |   7 +
 arch/arm/dts/Makefile                  |   2 +
 arch/arm/dts/imx6ull-14x14-evk.dts     | 527 +++++++++++++++++++++++++++++++++
 board/freescale/mx6ullevk/Kconfig      |  12 +
 board/freescale/mx6ullevk/MAINTAINERS  |   6 +
 board/freescale/mx6ullevk/Makefile     |   6 +
 board/freescale/mx6ullevk/imximage.cfg | 116 ++++++++
 board/freescale/mx6ullevk/mx6ullevk.c  |  99 +++++++
 configs/mx6ull_14x14_evk_defconfig     |  30 ++
 include/configs/mx6ullevk.h            | 180 +++++++++++
 10 files changed, 985 insertions(+)
 create mode 100644 arch/arm/dts/imx6ull-14x14-evk.dts
 create mode 100644 board/freescale/mx6ullevk/Kconfig
 create mode 100644 board/freescale/mx6ullevk/MAINTAINERS
 create mode 100644 board/freescale/mx6ullevk/Makefile
 create mode 100644 board/freescale/mx6ullevk/imximage.cfg
 create mode 100644 board/freescale/mx6ullevk/mx6ullevk.c
 create mode 100644 configs/mx6ull_14x14_evk_defconfig
 create mode 100644 include/configs/mx6ullevk.h

Comments

Jagan Teki Sept. 7, 2016, 2:51 p.m. UTC | #1 
On Thu, Aug 11, 2016 at 11:32 AM, Peng Fan <van.freenix@gmail.com> wrote:
> Add i.MX6ULL EVK board support:
> Add device tree file, which is copied from NXP Linux.
> Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
> The uart iomux settings are still keeped in board file.
>
> Boot Log:
> U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)
>
> CPU:   Freescale i.MX6ULL rev1.0 at 396MHz
> CPU:   Commercial temperature grade (0C to 95C) at 15C
> Reset cause: POR
> Model: Freescale i.MX6 ULL 14x14 EVK Board
> Board: MX6ULL 14x14 EVK
> DRAM:  512 MiB
> MMC:   initialized IMX pinctrl driver
> FSL_SDHC: 0, FSL_SDHC: 1

<snip>

> diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
> new file mode 100644
> index 0000000..489bf21
> --- /dev/null
> +++ b/board/freescale/mx6ullevk/mx6ullevk.c
> @@ -0,0 +1,99 @@
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <asm/io.h>
> +#include <common.h>
> +#include <fsl_esdhc.h>
> +#include <linux/sizes.h>
> +#include <mmc.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
> +       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
> +       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> +
> +int dram_init(void)
> +{
> +       gd->ram_size = imx_ddr_size();
> +
> +       return 0;
> +}
> +
> +static iomux_v3_cfg_t const uart1_pads[] = {
> +       MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +       MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> +       imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> +       return devno;
> +}
> +
> +int mmc_map_to_kernel_blk(int devno)
> +{
> +       return devno;
> +}
> +
> +int board_early_init_f(void)
> +{
> +       setup_iomux_uart();

Don't we need iomux settings for sdhc? I guess pinctrl for SD not
supporting now.

thanks!
Peng Fan Sept. 8, 2016, 1:35 a.m. UTC | #2 
Hi Jagan,
On Wed, Sep 07, 2016 at 08:21:07PM +0530, Jagan Teki wrote:
>On Thu, Aug 11, 2016 at 11:32 AM, Peng Fan <van.freenix@gmail.com> wrote:
>> Add i.MX6ULL EVK board support:
>> Add device tree file, which is copied from NXP Linux.
>> Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
>> The uart iomux settings are still keeped in board file.
>>
>> Boot Log:
>> U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)
>>
>> CPU:   Freescale i.MX6ULL rev1.0 at 396MHz
>> CPU:   Commercial temperature grade (0C to 95C) at 15C
>> Reset cause: POR
>> Model: Freescale i.MX6 ULL 14x14 EVK Board
>> Board: MX6ULL 14x14 EVK
>> DRAM:  512 MiB
>> MMC:   initialized IMX pinctrl driver
>> FSL_SDHC: 0, FSL_SDHC: 1
>
><snip>
>
>> diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
>> new file mode 100644
>> index 0000000..489bf21
>> --- /dev/null
>> +++ b/board/freescale/mx6ullevk/mx6ullevk.c
>> @@ -0,0 +1,99 @@
>> +/*
>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/iomux.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <asm/arch/crm_regs.h>
>> +#include <asm/arch/mx6-pins.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <asm/gpio.h>
>> +#include <asm/imx-common/iomux-v3.h>
>> +#include <asm/imx-common/boot_mode.h>
>> +#include <asm/io.h>
>> +#include <common.h>
>> +#include <fsl_esdhc.h>
>> +#include <linux/sizes.h>
>> +#include <mmc.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
>> +       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
>> +       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
>> +
>> +int dram_init(void)
>> +{
>> +       gd->ram_size = imx_ddr_size();
>> +
>> +       return 0;
>> +}
>> +
>> +static iomux_v3_cfg_t const uart1_pads[] = {
>> +       MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>> +       MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>> +};
>> +
>> +static void setup_iomux_uart(void)
>> +{
>> +       imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
>> +}
>> +
>> +int board_mmc_get_env_dev(int devno)
>> +{
>> +       return devno;
>> +}
>> +
>> +int mmc_map_to_kernel_blk(int devno)
>> +{
>> +       return devno;
>> +}
>> +
>> +int board_early_init_f(void)
>> +{
>> +       setup_iomux_uart();
>
>Don't we need iomux settings for sdhc? I guess pinctrl for SD not
>supporting now.

The pinctrl driver will configure the pinmux, no need to add iomux settings
in board file. In this patchset, I enabled PINCTRL, DM_MMC, DM_GPIO and etc.

Thanks,
Peng.

>
>thanks!
>-- 
>Jagan Teki
>Free Software Engineer | www.openedev.com
>U-Boot, Linux | Upstream Maintainer
>Hyderabad, India.
Jagan Teki Sept. 13, 2016, 7:11 p.m. UTC | #3 
Hi Peng,

On Thu, Sep 8, 2016 at 7:05 AM, Peng Fan <van.freenix@gmail.com> wrote:
> Hi Jagan,
> On Wed, Sep 07, 2016 at 08:21:07PM +0530, Jagan Teki wrote:
>>On Thu, Aug 11, 2016 at 11:32 AM, Peng Fan <van.freenix@gmail.com> wrote:
>>> Add i.MX6ULL EVK board support:
>>> Add device tree file, which is copied from NXP Linux.
>>> Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
>>> The uart iomux settings are still keeped in board file.
>>>
>>> Boot Log:
>>> U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)
>>>
>>> CPU:   Freescale i.MX6ULL rev1.0 at 396MHz
>>> CPU:   Commercial temperature grade (0C to 95C) at 15C
>>> Reset cause: POR
>>> Model: Freescale i.MX6 ULL 14x14 EVK Board
>>> Board: MX6ULL 14x14 EVK
>>> DRAM:  512 MiB
>>> MMC:   initialized IMX pinctrl driver
>>> FSL_SDHC: 0, FSL_SDHC: 1
>>
>><snip>
>>
>>> diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
>>> new file mode 100644
>>> index 0000000..489bf21
>>> --- /dev/null
>>> +++ b/board/freescale/mx6ullevk/mx6ullevk.c
>>> @@ -0,0 +1,99 @@
>>> +/*
>>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>>> + *
>>> + * SPDX-License-Identifier:    GPL-2.0+
>>> + */
>>> +
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/arch/iomux.h>
>>> +#include <asm/arch/imx-regs.h>
>>> +#include <asm/arch/crm_regs.h>
>>> +#include <asm/arch/mx6-pins.h>
>>> +#include <asm/arch/sys_proto.h>
>>> +#include <asm/gpio.h>
>>> +#include <asm/imx-common/iomux-v3.h>
>>> +#include <asm/imx-common/boot_mode.h>
>>> +#include <asm/io.h>
>>> +#include <common.h>
>>> +#include <fsl_esdhc.h>
>>> +#include <linux/sizes.h>
>>> +#include <mmc.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
>>> +       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
>>> +       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
>>> +
>>> +int dram_init(void)
>>> +{
>>> +       gd->ram_size = imx_ddr_size();

Is this common call for all imx soc's to get the ddr size? because I
observed incorrect size when I call this function.

>>> +
>>> +       return 0;
>>> +}
>>> +
>>> +static iomux_v3_cfg_t const uart1_pads[] = {
>>> +       MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>> +       MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>> +};
>>> +
>>> +static void setup_iomux_uart(void)
>>> +{
>>> +       imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
>>> +}
>>> +
>>> +int board_mmc_get_env_dev(int devno)
>>> +{
>>> +       return devno;
>>> +}
>>> +
>>> +int mmc_map_to_kernel_blk(int devno)
>>> +{
>>> +       return devno;
>>> +}
>>> +
>>> +int board_early_init_f(void)
>>> +{
>>> +       setup_iomux_uart();
>>
>>Don't we need iomux settings for sdhc? I guess pinctrl for SD not
>>supporting now.
>
> The pinctrl driver will configure the pinmux, no need to add iomux settings
> in board file. In this patchset, I enabled PINCTRL, DM_MMC, DM_GPIO and etc.

Yeah, but the uart pinx mux are still in board file right?
Fabio Estevam Sept. 13, 2016, 7:43 p.m. UTC | #4 
Hi Jagan,

On Tue, Sep 13, 2016 at 4:11 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:

>>>> +int dram_init(void)
>>>> +{
>>>> +       gd->ram_size = imx_ddr_size();
>
> Is this common call for all imx soc's to get the ddr size? because I
> observed incorrect size when I call this function.

Yes, if you get incorrect size when using this function, it means that
your DDR initialization is incorrect.
Peng Fan Sept. 14, 2016, 1:21 a.m. UTC | #5 
Hi Jagan,
On Wed, Sep 14, 2016 at 12:41:17AM +0530, Jagan Teki wrote:
>Hi Peng,
>
>On Thu, Sep 8, 2016 at 7:05 AM, Peng Fan <van.freenix@gmail.com> wrote:
>> Hi Jagan,
>> On Wed, Sep 07, 2016 at 08:21:07PM +0530, Jagan Teki wrote:
>>>On Thu, Aug 11, 2016 at 11:32 AM, Peng Fan <van.freenix@gmail.com> wrote:
>>>> Add i.MX6ULL EVK board support:
>>>> Add device tree file, which is copied from NXP Linux.
>>>> Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
>>>> The uart iomux settings are still keeped in board file.
>>>>
>>>> Boot Log:
>>>> U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)
>>>>
>>>> CPU:   Freescale i.MX6ULL rev1.0 at 396MHz
>>>> CPU:   Commercial temperature grade (0C to 95C) at 15C
>>>> Reset cause: POR
>>>> Model: Freescale i.MX6 ULL 14x14 EVK Board
>>>> Board: MX6ULL 14x14 EVK
>>>> DRAM:  512 MiB
>>>> MMC:   initialized IMX pinctrl driver
>>>> FSL_SDHC: 0, FSL_SDHC: 1
>>>
>>><snip>
>>>
>>>> diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
>>>> new file mode 100644
>>>> index 0000000..489bf21
>>>> --- /dev/null
>>>> +++ b/board/freescale/mx6ullevk/mx6ullevk.c
>>>> @@ -0,0 +1,99 @@
>>>> +/*
>>>> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
>>>> + *
>>>> + * SPDX-License-Identifier:    GPL-2.0+
>>>> + */
>>>> +
>>>> +#include <asm/arch/clock.h>
>>>> +#include <asm/arch/iomux.h>
>>>> +#include <asm/arch/imx-regs.h>
>>>> +#include <asm/arch/crm_regs.h>
>>>> +#include <asm/arch/mx6-pins.h>
>>>> +#include <asm/arch/sys_proto.h>
>>>> +#include <asm/gpio.h>
>>>> +#include <asm/imx-common/iomux-v3.h>
>>>> +#include <asm/imx-common/boot_mode.h>
>>>> +#include <asm/io.h>
>>>> +#include <common.h>
>>>> +#include <fsl_esdhc.h>
>>>> +#include <linux/sizes.h>
>>>> +#include <mmc.h>
>>>> +
>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>> +
>>>> +#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
>>>> +       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
>>>> +       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
>>>> +
>>>> +int dram_init(void)
>>>> +{
>>>> +       gd->ram_size = imx_ddr_size();
>
>Is this common call for all imx soc's to get the ddr size? because I
>observed incorrect size when I call this function.
>
>>>> +
>>>> +       return 0;
>>>> +}
>>>> +
>>>> +static iomux_v3_cfg_t const uart1_pads[] = {
>>>> +       MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>>> +       MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
>>>> +};
>>>> +
>>>> +static void setup_iomux_uart(void)
>>>> +{
>>>> +       imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
>>>> +}
>>>> +
>>>> +int board_mmc_get_env_dev(int devno)
>>>> +{
>>>> +       return devno;
>>>> +}
>>>> +
>>>> +int mmc_map_to_kernel_blk(int devno)
>>>> +{
>>>> +       return devno;
>>>> +}
>>>> +
>>>> +int board_early_init_f(void)
>>>> +{
>>>> +       setup_iomux_uart();
>>>
>>>Don't we need iomux settings for sdhc? I guess pinctrl for SD not
>>>supporting now.
>>
>> The pinctrl driver will configure the pinmux, no need to add iomux settings
>> in board file. In this patchset, I enabled PINCTRL, DM_MMC, DM_GPIO and etc.
>
>Yeah, but the uart pinx mux are still in board file right?

I did not enable DM UART. Since lowlevel debug not implemented for i.MX6,
I need to initialize uart as early as possible. When lowlevel debug
implemented, we could switch to use pinctrl to initialze uart pinmux and
use DM UART.
So now I keep the uart pinmux settings in board file.

Regards,
Peng.
>
>-- 
>Jagan Teki
>Free Software Engineer | www.openedev.com
>U-Boot, Linux | Upstream Maintainer
>Hyderabad, India.
Jagan Teki Sept. 15, 2016, 8:48 p.m. UTC | #6 
Hi Fabio,

On Wed, Sep 14, 2016 at 1:13 AM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Jagan,
>
> On Tue, Sep 13, 2016 at 4:11 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>
>>>>> +int dram_init(void)
>>>>> +{
>>>>> +       gd->ram_size = imx_ddr_size();
>>
>> Is this common call for all imx soc's to get the ddr size? because I
>> observed incorrect size when I call this function.
>
> Yes, if you get incorrect size when using this function, it means that
> your DDR initialization is incorrect.

OK, and I ran imx6 ddr calibration stress test[1] but observed data
abort. the objdump doesn't show any of these address, can you please
help me how can I proceed further?

icorem6qdl> fatload mmc 0:1 0x10000000 ddr-stress-test-mx6dq.bin
reading ddr-stress-test-mx6dq.bin
87520 bytes read in 26 ms (3.2 MiB/s)
icorem6qdl> go 0x10000000
## Starting application at 0x10000000 ...
data abort
pc : [<00907060>]          lr : [<8ff873fb>]
reloc pc : [<88182060>]    lr : [<178023fb>]
sp : 8ef7c458  ip : 00000010     fp : 00000002
r10: 8ffb8914  r9 : 8ef84ee8     r8 : 8ef87cf0
r7 : 8ff873d1  r6 : 10000000     r5 : 00000002  r4 : 8ef87cf4
r3 : 10000000  r2 : 8ef87cf4     r1 : 8ef87cf4  r0 : 00000001
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

[1] https://community.nxp.com/docs/DOC-96412

thanks!
Fabio Estevam Sept. 17, 2016, 12:14 a.m. UTC | #7 
On Thu, Sep 15, 2016 at 5:48 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:

> OK, and I ran imx6 ddr calibration stress test[1] but observed data
> abort. the objdump doesn't show any of these address, can you please
> help me how can I proceed further?
>
> icorem6qdl> fatload mmc 0:1 0x10000000 ddr-stress-test-mx6dq.bin
> reading ddr-stress-test-mx6dq.bin
> 87520 bytes read in 26 ms (3.2 MiB/s)
> icorem6qdl> go 0x10000000

This is wrong. You cannot run this code from DDR. You should run from
internal RAM instead.

From https://community.nxp.com/docs/DOC-105652:

"When download DDR Stress Tool by uboot, please copy the
ddr-test-uboot-jtag-mx???.bin to SD card and load it to IRAM by
'fatload' uboot command. For i.MX6, please load the binary to
0x00907000. For i.MX7D, please load the binary to 0x00910000"
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 09db849..84fa3eb 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -133,6 +133,12 @@  config TARGET_MX6UL_14X14_EVK
 	select DM_THERMAL
 	select SUPPORT_SPL
 
+config TARGET_MX6ULL_14X14_EVK
+	bool "Support mx6ull_14x14_evk"
+	select MX6ULL
+	select DM
+	select DM_THERMAL
+
 config TARGET_NITROGEN6X
 	bool "nitrogen6x"
 
@@ -221,6 +227,7 @@  source "board/freescale/mx6slevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
+source "board/freescale/mx6ullevk/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d93fabc..91a533f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -265,6 +265,8 @@  dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 	vf610-twr.dtb \
 	pcm052.dtb
 
+dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb
+
 dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
 	k2l-evm.dtb \
 	k2e-evm.dtb \
diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts
new file mode 100644
index 0000000..375bd4e
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-evk.dts
@@ -0,0 +1,527 @@ 
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ull.dtsi"
+
+/ {
+	model = "Freescale i.MX6 ULL 14x14 EVK Board";
+	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_can_3v3: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "can-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_sd1_vmmc: regulator@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_gpio_dvfs: regulator-gpio {
+			compatible = "regulator-gpio";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_dvfs>;
+			regulator-min-microvolt = <1300000>;
+			regulator-max-microvolt = <1400000>;
+			regulator-name = "gpio_dvfs";
+			regulator-type = "voltage";
+			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+			states = <1300000 0x1 1400000 0x0>;
+		};
+	};
+
+	spi4 {
+		compatible = "spi-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_spi4>;
+		status = "okay";
+		gpio-sck = <&gpio5 11 0>;
+		gpio-mosi = <&gpio5 10 0>;
+		cs-gpios = <&gpio5 7 0>;
+		num-chipselects = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		gpio_spi: gpio_spi@0 {
+			compatible = "fairchild,74hc595";
+			gpio-controller;
+			oe-gpios = <&gpio5 8 0>;
+			#gpio-cells = <2>;
+			reg = <0>;
+			registers-number = <1>;
+			registers-default = /bits/ 8 <0x57>;
+			spi-max-frequency = <100000>;
+		};
+	};
+};
+
+&cpu0 {
+	arm-supply = <&reg_arm>;
+	soc-supply = <&reg_soc>;
+	dc-supply = <&reg_gpio_dvfs>;
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <786432000>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
+
+&gpc {
+	fsl,cpu_pupscr_sw2iso = <0x1>;
+	fsl,cpu_pupscr_sw = <0x0>;
+	fsl,cpu_pdnscr_iso2sw = <0x1>;
+	fsl,cpu_pdnscr_iso = <0x1>;
+	fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	mag3110@0e {
+		compatible = "fsl,mag3110";
+		reg = <0x0e>;
+		position = <2>;
+	};
+
+	fxls8471@1e {
+		compatible = "fsl,fxls8471";
+		reg = <0x1e>;
+		position = <0>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <0 8>;
+	};
+};
+
+&i2c2 {
+	clock_frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+	imx6ul-evk {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
+				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
+				MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+			>;
+		};
+
+		pinctrl_csi1: csi1grp {
+			fsl,pins = <
+				MX6UL_PAD_CSI_MCLK__CSI_MCLK		0x1b088
+				MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK	0x1b088
+				MX6UL_PAD_CSI_VSYNC__CSI_VSYNC		0x1b088
+				MX6UL_PAD_CSI_HSYNC__CSI_HSYNC		0x1b088
+				MX6UL_PAD_CSI_DATA00__CSI_DATA02	0x1b088
+				MX6UL_PAD_CSI_DATA01__CSI_DATA03	0x1b088
+				MX6UL_PAD_CSI_DATA02__CSI_DATA04	0x1b088
+				MX6UL_PAD_CSI_DATA03__CSI_DATA05	0x1b088
+				MX6UL_PAD_CSI_DATA04__CSI_DATA06	0x1b088
+				MX6UL_PAD_CSI_DATA05__CSI_DATA07	0x1b088
+				MX6UL_PAD_CSI_DATA06__CSI_DATA08	0x1b088
+				MX6UL_PAD_CSI_DATA07__CSI_DATA09	0x1b088
+			>;
+		};
+
+		pinctrl_enet1: enet1grp {
+			fsl,pins = <
+				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+				MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
+			>;
+		};
+
+		pinctrl_flexcan1: flexcan1grp{
+			fsl,pins = <
+				MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
+				MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
+			>;
+		};
+
+		pinctrl_flexcan2: flexcan2grp{
+			fsl,pins = <
+				MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
+				MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+				MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+				MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+				MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+				MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+				MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+				MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+				MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+				MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+				MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+				MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+				MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+				MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+				MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+				MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+				MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+				MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+				MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+				MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+				MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+				MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+				MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+				MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+				MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+				MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+				MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
+				MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+				MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+				MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+			>;
+		};
+
+		pinctrl_pwm1: pwm1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
+				MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+				MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
+				MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
+				MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
+				MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
+				MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
+				MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
+				MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2dte: uart2dtegrp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX	0x1b0b1
+				MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX	0x1b0b1
+				MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS	0x1b0b1
+				MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS	0x1b0b1
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
+			>;
+		};
+	};
+};
+
+&iomuxc_snvs {
+	pinctrl-names = "default_snvs";
+        pinctrl-0 = <&pinctrl_hog_2>;
+        imx6ul-evk {
+		pinctrl_hog_2: hoggrp-2 {
+                        fsl,pins = <
+                                MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
+                        >;
+                };
+
+		pinctrl_dvfs: dvfsgrp {
+                        fsl,pins = <
+                                MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
+                        >;
+                };
+
+		pinctrl_lcdif_reset: lcdifresetgrp {
+                        fsl,pins = <
+                                /* used for lcd reset */
+                                MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
+                        >;
+                };
+
+		pinctrl_spi4: spi4grp {
+                        fsl,pins = <
+                                MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
+                                MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
+                                MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x70a1
+                                MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x80000000
+                        >;
+                };
+
+                pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
+                        fsl,pins = <
+                                MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04   0x17059
+                        >;
+                };
+        };
+};
+
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl
+		     &pinctrl_lcdif_reset>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+			clock-frequency = <9200000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <8>;
+			hback-porch = <4>;
+			hsync-len = <41>;
+			vback-porch = <2>;
+			vfront-porch = <4>;
+			vsync-len = <10>;
+
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+	ddrsmp=<0>;
+
+	flash0: n25q256a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <0>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	fsl,uart-has-rtscts;
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode; */
+	/* pinctrl-0 = <&pinctrl_uart2dte>; */
+	status = "okay";
+};
+
+&usbotg1 {
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usbphy1 {
+	tx-d-cal = <0x5>;
+};
+
+&usbphy2 {
+	tx-d-cal = <0x5>;
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	no-1-8-v;
+	non-removable;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,wdog_b;
+};
diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig
new file mode 100644
index 0000000..7eec497
--- /dev/null
+++ b/board/freescale/mx6ullevk/Kconfig
@@ -0,0 +1,12 @@ 
+if TARGET_MX6ULL_14X14_EVK
+
+config SYS_BOARD
+	default "mx6ullevk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6ullevk"
+
+endif
diff --git a/board/freescale/mx6ullevk/MAINTAINERS b/board/freescale/mx6ullevk/MAINTAINERS
new file mode 100644
index 0000000..4137674
--- /dev/null
+++ b/board/freescale/mx6ullevk/MAINTAINERS
@@ -0,0 +1,6 @@ 
+MX6ULLEVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6ullevk/
+F:	include/configs/mx6ullevk.h
+F:	configs/mx6ull_14x14_evk_defconfig
diff --git a/board/freescale/mx6ullevk/Makefile b/board/freescale/mx6ullevk/Makefile
new file mode 100644
index 0000000..c64fba4
--- /dev/null
+++ b/board/freescale/mx6ullevk/Makefile
@@ -0,0 +1,6 @@ 
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6ullevk.o
diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg
new file mode 100644
index 0000000..4604b62
--- /dev/null
+++ b/board/freescale/mx6ullevk/imximage.cfg
@@ -0,0 +1,116 @@ 
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM	qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ullevk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x000C0030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000004
+DATA 4 0x021B083C 0x41640158
+DATA 4 0x021B0848 0x40403237
+DATA 4 0x021B0850 0x40403C33
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00944009
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
new file mode 100644
index 0000000..489bf21
--- /dev/null
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -0,0 +1,99 @@ 
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+	return devno;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	setenv("board_name", "EVK");
+	setenv("board_rev", "14X14");
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6ULL 14x14 EVK\n");
+
+	return 0;
+}
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
new file mode 100644
index 0000000..a106b5d
--- /dev/null
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -0,0 +1,30 @@ 
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_SPI=y
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
new file mode 100644
index 0000000..ccce954
--- /dev/null
+++ b/include/configs/mx6ullevk.h
@@ -0,0 +1,180 @@ 
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MX6ULLEVK_CONFIG_H
+#define __MX6ULLEVK_CONFIG_H
+
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/imx-common/gpio.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+#define PHYS_SDRAM_SIZE	SZ_512M
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* NAND pin conflicts with usdhc2 */
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+#endif
+
+/* I2C configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6ull-14x14-evk.dtb\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
+
+#define CONFIG_CMD_BMODE
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IOMUX_LPSR
+
+#define CONFIG_SOFT_SPI
+
+#endif