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GET /api/patches/817579/?format=api
{ "id": 817579, "url": "http://patchwork.ozlabs.org/api/patches/817579/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-19-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506092407-26985-19-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-22T15:00:05", "name": "[18/20] target/arm: Implement BLXNS", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1c372215341697596680da8c5c2892e255118d35", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-19-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 4650, "url": "http://patchwork.ozlabs.org/api/series/4650/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650", "date": "2017-09-22T14:59:47", "name": "ARM v8M: exception entry, exit and security", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4650/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817579/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817579/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzHCc4Pw7z9sNw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 23 Sep 2017 01:17:32 +1000 (AEST)", "from localhost ([::1]:59423 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dvPhq-0006jJ-Kl\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:17:30 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:47329)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQm-00089V-1x\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:53 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQk-0004M9-VZ\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:52 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37588)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQg-0004EW-Ek; Fri, 22 Sep 2017 10:59:46 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQc-0007G2-7Y; Fri, 22 Sep 2017 15:59:42 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Fri, 22 Sep 2017 16:00:05 +0100", "Message-Id": "<1506092407-26985-19-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "References": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Implement the BLXNS instruction, which allows secure code to\ncall non-secure code.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/helper.h | 1 +\n target/arm/internals.h | 1 +\n target/arm/helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++\n target/arm/translate.c | 17 +++++++++++++--\n 4 files changed, 76 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/arm/helper.h b/target/arm/helper.h\nindex 64afbac..2cf6f74 100644\n--- a/target/arm/helper.h\n+++ b/target/arm/helper.h\n@@ -64,6 +64,7 @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32)\n DEF_HELPER_2(v7m_mrs, i32, env, i32)\n \n DEF_HELPER_2(v7m_bxns, void, env, i32)\n+DEF_HELPER_2(v7m_blxns, void, env, i32)\n \n DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)\n DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)\ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex fd9a7e8..1746737 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -60,6 +60,7 @@ static inline bool excp_is_internal(int excp)\n FIELD(V7M_CONTROL, NPRIV, 0, 1)\n FIELD(V7M_CONTROL, SPSEL, 1, 1)\n FIELD(V7M_CONTROL, FPCA, 2, 1)\n+FIELD(V7M_CONTROL, SFPA, 3, 1)\n \n /* Bit definitions for v7M exception return payload */\n FIELD(V7M_EXCRET, ES, 0, 1)\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 8df819d..30dc2a9 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -5890,6 +5890,12 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)\n g_assert_not_reached();\n }\n \n+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)\n+{\n+ /* translate.c should never generate calls here in user-only mode */\n+ g_assert_not_reached();\n+}\n+\n void switch_mode(CPUARMState *env, int mode)\n {\n ARMCPU *cpu = arm_env_get_cpu(env);\n@@ -6182,6 +6188,59 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)\n env->regs[15] = dest & ~1;\n }\n \n+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)\n+{\n+ /* Handle v7M BLXNS:\n+ * - bit 0 of the destination address is the target security state\n+ */\n+\n+ /* At this point regs[15] is the address just after the BLXNS */\n+ uint32_t nextinst = env->regs[15] | 1;\n+ uint32_t sp = env->regs[13] - 8;\n+ uint32_t saved_psr;\n+\n+ /* translate.c will have made BLXNS UNDEF unless we're secure */\n+ assert(env->v7m.secure);\n+\n+ if (dest & 1) {\n+ /* target is Secure, so this is just a normal BLX,\n+ * except that the low bit doesn't indicate Thumb/not.\n+ */\n+ env->regs[14] = nextinst;\n+ env->thumb = 1;\n+ env->regs[15] = dest & ~1;\n+ return;\n+ }\n+\n+ /* Target is non-secure: first push a stack frame */\n+ if (!QEMU_IS_ALIGNED(sp, 8)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"BLXNS with misaligned SP is UNPREDICTABLE\\n\");\n+ }\n+\n+ saved_psr = env->v7m.exception;\n+ if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {\n+ saved_psr |= XPSR_SFPA;\n+ }\n+\n+ /* Note that these stores can throw exceptions on MPU faults */\n+ cpu_stl_data(env, sp, nextinst);\n+ cpu_stl_data(env, sp + 4, saved_psr);\n+\n+ env->regs[13] = sp;\n+ env->regs[14] = 0xfeffffff;\n+ if (arm_v7m_is_handler_mode(env)) {\n+ /* Write a dummy value to IPSR, to avoid leaking the current secure\n+ * exception number to non-secure code. This is guaranteed not\n+ * to cause write_v7m_exception() to actually change stacks.\n+ */\n+ write_v7m_exception(env, 1);\n+ }\n+ switch_v7m_security_state(env, dest & 1);\n+ env->thumb = 1;\n+ env->regs[15] = dest & ~1;\n+}\n+\n static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,\n bool spsel)\n {\ndiff --git a/target/arm/translate.c b/target/arm/translate.c\nindex ab1a12a..53694bb 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -1013,6 +1013,20 @@ static inline void gen_bxns(DisasContext *s, int rm)\n s->base.is_jmp = DISAS_EXIT;\n }\n \n+static inline void gen_blxns(DisasContext *s, int rm)\n+{\n+ TCGv_i32 var = load_reg(s, rm);\n+\n+ /* We don't need to sync condexec state, for the same reason as blxns.\n+ * We do however need to set the PC, because the blxns helper reads it.\n+ * The blxns helper may throw an exception.\n+ */\n+ gen_set_pc_im(s, s->pc);\n+ gen_helper_v7m_blxns(cpu_env, var);\n+ tcg_temp_free_i32(var);\n+ s->base.is_jmp = DISAS_EXIT;\n+}\n+\n /* Variant of store_reg which uses branch&exchange logic when storing\n to r15 in ARM architecture v7 and above. The source must be a temporary\n and will be marked as dead. */\n@@ -11221,8 +11235,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)\n goto undef;\n }\n if (link) {\n- /* BLXNS: not yet implemented */\n- goto undef;\n+ gen_blxns(s, rm);\n } else {\n gen_bxns(s, rm);\n }\n", "prefixes": [ "18/20" ] }