[{"id":1780602,"web_url":"http://patchwork.ozlabs.org/comment/1780602/","msgid":"<2fc8208b-a3d6-001d-a60d-fe3250f7befe@amsat.org>","list_archive_url":null,"date":"2017-10-05T13:07:05","subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 18/20] target/arm: Implement\n\tBLXNS","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 09/22/2017 12:00 PM, Peter Maydell wrote:\n> Implement the BLXNS instruction, which allows secure code to\n> call non-secure code.\n> \n> Signed-off-by: Peter Maydell \n\nAcked-by: Philippe Mathieu-Daudé \n\n> ---\n> target/arm/helper.h | 1 +\n> target/arm/internals.h | 1 +\n> target/arm/helper.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++\n> target/arm/translate.c | 17 +++++++++++++--\n> 4 files changed, 76 insertions(+), 2 deletions(-)\n> \n> diff --git a/target/arm/helper.h b/target/arm/helper.h\n> index 64afbac..2cf6f74 100644\n> --- a/target/arm/helper.h\n> +++ b/target/arm/helper.h\n> @@ -64,6 +64,7 @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32)\n> DEF_HELPER_2(v7m_mrs, i32, env, i32)\n> \n> DEF_HELPER_2(v7m_bxns, void, env, i32)\n> +DEF_HELPER_2(v7m_blxns, void, env, i32)\n> \n> DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)\n> DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)\n> diff --git a/target/arm/internals.h b/target/arm/internals.h\n> index fd9a7e8..1746737 100644\n> --- a/target/arm/internals.h\n> +++ b/target/arm/internals.h\n> @@ -60,6 +60,7 @@ static inline bool excp_is_internal(int excp)\n> FIELD(V7M_CONTROL, NPRIV, 0, 1)\n> FIELD(V7M_CONTROL, SPSEL, 1, 1)\n> FIELD(V7M_CONTROL, FPCA, 2, 1)\n> +FIELD(V7M_CONTROL, SFPA, 3, 1)\n> \n> /* Bit definitions for v7M exception return payload */\n> FIELD(V7M_EXCRET, ES, 0, 1)\n> diff --git a/target/arm/helper.c b/target/arm/helper.c\n> index 8df819d..30dc2a9 100644\n> --- a/target/arm/helper.c\n> +++ b/target/arm/helper.c\n> @@ -5890,6 +5890,12 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)\n> g_assert_not_reached();\n> }\n> \n> +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)\n> +{\n> + /* translate.c should never generate calls here in user-only mode */\n> + g_assert_not_reached();\n> +}\n> +\n> void switch_mode(CPUARMState *env, int mode)\n> {\n> ARMCPU *cpu = arm_env_get_cpu(env);\n> @@ -6182,6 +6188,59 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)\n> env->regs[15] = dest & ~1;\n> }\n> \n> +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)\n> +{\n> + /* Handle v7M BLXNS:\n> + * - bit 0 of the destination address is the target security state\n> + */\n> +\n> + /* At this point regs[15] is the address just after the BLXNS */\n> + uint32_t nextinst = env->regs[15] | 1;\n> + uint32_t sp = env->regs[13] - 8;\n> + uint32_t saved_psr;\n> +\n> + /* translate.c will have made BLXNS UNDEF unless we're secure */\n> + assert(env->v7m.secure);\n> +\n> + if (dest & 1) {\n> + /* target is Secure, so this is just a normal BLX,\n> + * except that the low bit doesn't indicate Thumb/not.\n> + */\n> + env->regs[14] = nextinst;\n> + env->thumb = 1;\n> + env->regs[15] = dest & ~1;\n> + return;\n> + }\n> +\n> + /* Target is non-secure: first push a stack frame */\n> + if (!QEMU_IS_ALIGNED(sp, 8)) {\n> + qemu_log_mask(LOG_GUEST_ERROR,\n> + \"BLXNS with misaligned SP is UNPREDICTABLE\\n\");\n> + }\n> +\n> + saved_psr = env->v7m.exception;\n> + if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {\n> + saved_psr |= XPSR_SFPA;\n> + }\n> +\n> + /* Note that these stores can throw exceptions on MPU faults */\n> + cpu_stl_data(env, sp, nextinst);\n> + cpu_stl_data(env, sp + 4, saved_psr);\n> +\n> + env->regs[13] = sp;\n> + env->regs[14] = 0xfeffffff;\n> + if (arm_v7m_is_handler_mode(env)) {\n> + /* Write a dummy value to IPSR, to avoid leaking the current secure\n> + * exception number to non-secure code. This is guaranteed not\n> + * to cause write_v7m_exception() to actually change stacks.\n> + */\n> + write_v7m_exception(env, 1);\n> + }\n> + switch_v7m_security_state(env, dest & 1);\n> + env->thumb = 1;\n> + env->regs[15] = dest & ~1;\n> +}\n> +\n> static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,\n> bool spsel)\n> {\n> diff --git a/target/arm/translate.c b/target/arm/translate.c\n> index ab1a12a..53694bb 100644\n> --- a/target/arm/translate.c\n> +++ b/target/arm/translate.c\n> @@ -1013,6 +1013,20 @@ static inline void gen_bxns(DisasContext *s, int rm)\n> s->base.is_jmp = DISAS_EXIT;\n> }\n> \n> +static inline void gen_blxns(DisasContext *s, int rm)\n> +{\n> + TCGv_i32 var = load_reg(s, rm);\n> +\n> + /* We don't need to sync condexec state, for the same reason as blxns.\n> + * We do however need to set the PC, because the blxns helper reads it.\n> + * The blxns helper may throw an exception.\n> + */\n> + gen_set_pc_im(s, s->pc);\n> + gen_helper_v7m_blxns(cpu_env, var);\n> + tcg_temp_free_i32(var);\n> + s->base.is_jmp = DISAS_EXIT;\n> +}\n> +\n> /* Variant of store_reg which uses branch&exchange logic when storing\n> to r15 in ARM architecture v7 and above. The source must be a temporary\n> and will be marked as dead. */\n> @@ -11221,8 +11235,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)\n> goto undef;\n> }\n> if (link) {\n> - /* BLXNS: not yet implemented */\n> - goto undef;\n> + gen_blxns(s, rm);\n> } else {\n> gen_bxns(s, rm);\n> }\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"owez1xNJ\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7Ck04hbgz9sDB\n\tfor ;\n\tFri, 6 Oct 2017 00:07:51 +1100 (AEDT)","from localhost ([::1]:39767 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e05sQ-0004rq-Uy\n\tfor incoming@patchwork.ozlabs.org; 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\n\tThu, 05 Oct 2017 06:07:08 -0700 (PDT)","To":"Peter Maydell , qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-19-git-send-email-peter.maydell@linaro.org>","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Openpgp":"id=FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE;\n\turl=http://pgp.mit.edu/pks/lookup?op=get&search=0xE3E32C2CDEADC0DE","Message-ID":"<2fc8208b-a3d6-001d-a60d-fe3250f7befe@amsat.org>","Date":"Thu, 5 Oct 2017 10:07:05 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-19-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::241","Subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 18/20] target/arm: Implement\n\tBLXNS","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780914,"web_url":"http://patchwork.ozlabs.org/comment/1780914/","msgid":"","list_archive_url":null,"date":"2017-10-05T18:56:26","subject":"Re: [Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 11:00 AM, Peter Maydell wrote:\n> +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)\n> +{\n...\n> + if (dest & 1) {\n> + /* target is Secure, so this is just a normal BLX,\n> + * except that the low bit doesn't indicate Thumb/not.\n> + */\n> + env->regs[14] = nextinst;\n> + env->thumb = 1;\n> + env->regs[15] = dest & ~1;\n> + return;\n> + }\n...\n> + switch_v7m_security_state(env, dest & 1);\n> + env->thumb = 1;\n> + env->regs[15] = dest & ~1;\n\ndest & 1 is known to be 0.\n\n> +static inline void gen_blxns(DisasContext *s, int rm)\n> +{\n> + TCGv_i32 var = load_reg(s, rm);\n> +\n> + /* We don't need to sync condexec state, for the same reason as blxns.\n\ns/blxns/bxns/ ?\n\nOtherwise,\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-19-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::235","Subject":"Re: [Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780952,"web_url":"http://patchwork.ozlabs.org/comment/1780952/","msgid":"","list_archive_url":null,"date":"2017-10-05T19:40:40","subject":"Re: [Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 5 October 2017 at 19:56, Richard Henderson\n wrote:\n> On 09/22/2017 11:00 AM, Peter Maydell wrote:\n>> +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)\n>> +{\n> ...\n>> + if (dest & 1) {\n>> + /* target is Secure, so this is just a normal BLX,\n>> + * except that the low bit doesn't indicate Thumb/not.\n>> + */\n>> + env->regs[14] = nextinst;\n>> + env->thumb = 1;\n>> + env->regs[15] = dest & ~1;\n>> + return;\n>> + }\n> ...\n>> + switch_v7m_security_state(env, dest & 1);\n>> + env->thumb = 1;\n>> + env->regs[15] = dest & ~1;\n>\n> dest & 1 is known to be 0.\n\nYes. I liked the symmetry with the tail end of the v7m_bxns helper,\nwhich is conceptually doing the same thing, and assumed the\ncompiler would be smart enough not to generate unnecessary code.\n\n>> +static inline void gen_blxns(DisasContext *s, int rm)\n>> +{\n>> + TCGv_i32 var = load_reg(s, rm);\n>> +\n>> + /* We don't need to sync condexec state, for the same reason as blxns.\n>\n> s/blxns/bxns/ ?\n\nYes.\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"Ok8P12Qe\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7NSN2NTjz9t6W\n\tfor ;\n\tFri, 6 Oct 2017 06:41:39 +1100 (AEDT)","from localhost ([::1]:41791 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e0C1Y-00051t-OV\n\tfor incoming@patchwork.ozlabs.org; Thu, 05 Oct 2017 15:41:36 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:34081)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1e0C14-000504-0N\n\tfor qemu-devel@nongnu.org; Thu, 05 Oct 2017 15:41:06 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1e0C10-0000Rf-6w\n\tfor qemu-devel@nongnu.org; Thu, 05 Oct 2017 15:41:06 -0400","from mail-wm0-x22b.google.com ([2a00:1450:400c:c09::22b]:53436)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1e0C0z-0000P8-W8\n\tfor qemu-devel@nongnu.org; Thu, 05 Oct 2017 15:41:02 -0400","by mail-wm0-x22b.google.com with SMTP id q132so4180064wmd.2\n\tfor ; Thu, 05 Oct 2017 12:41:01 -0700 (PDT)","by 10.223.128.207 with HTTP; Thu, 5 Oct 2017 12:40:40 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=yHxj96lu0HWwF0nOUZ16bxGlAZ7tqVEufPppKI47hHU=;\n\tb=Ok8P12QeL/m/r8DtLs4nKnqd4YeQW/oIbLl6YyIaQ2D6/1X0I/3j3K9zEc/RgFmRLB\n\t05zIVejmE6PFW2sNz+a1bj7JwD6HiaBjAtAzFS+b7u+wGpczh7T1lF+PzcN/UWeL/gVV\n\tOnVDwJ3JihU2puZJmEajUJGpT2tW5R3Q2j4/w=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=yHxj96lu0HWwF0nOUZ16bxGlAZ7tqVEufPppKI47hHU=;\n\tb=aD4p8xvX1VJ6lFxT4FLTZk/YgMDrbxlOfolsbIZvGPNSpNRivsb+PUoE4MPiWbmRVQ\n\tQPPThFZYJ1qZdmqRp0qm18+6Dgs8dE8is2YYYEuGNoQaFEu2+Zt62A+DiBkIATg/8lN0\n\tp0UPJIlm2JzcCKrGPFH6cJlZrKocxeMNliF+TE2Uu/Y+c1sI6jwZfcx+impzF4b2rFjy\n\tID/wTZF/GJyEUn5mPYuZiBnEwMj+VvogoH6Yo8I7EmUVymRYuoyE+8k5Po7vhzbZP/5c\n\tSyc0HScY4mm79GywgWXjdIUJHE7HyAk2TlzPbb8CUmCaoa1JyVE90qjTI92X/U+QvTG/\n\tpynw==","X-Gm-Message-State":"AMCzsaWkypGFUU9/Z5Ir2G4K+wNOxyQf6i3UO4L9sbGPLimGO/8mCyl8\n\tDjO+HCy0jTsx5ceAnSoiMuOwSYpHx8kFld7PLsC3Qg==","X-Google-Smtp-Source":"AOwi7QBfxDYJiEYJAUKRnTEg6DXGh+uF97NbzZPOS3YnyfEz0/T1JUOopBhNcyEH/e05T0mhlCgx6mXxLAAS6R5LlpA=","X-Received":"by 10.28.236.203 with SMTP id h72mr157856wmi.147.1507232460876; \n\tThu, 05 Oct 2017 12:41:00 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-19-git-send-email-peter.maydell@linaro.org>\n\t","From":"Peter Maydell ","Date":"Thu, 5 Oct 2017 20:40:40 +0100","Message-ID":"","To":"Richard Henderson ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::22b","Subject":"Re: [Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-arm , QEMU Developers , \n\t\"patches@linaro.org\" ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]