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GET /api/patches/817341/?format=api
{ "id": 817341, "url": "http://patchwork.ozlabs.org/api/patches/817341/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170922072635.32105-4-wens@csie.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170922072635.32105-4-wens@csie.org>", "list_archive_url": null, "date": "2017-09-22T07:26:29", "name": "[U-Boot,3/9] sunxi: Fix USB PHY control register offset for A83T", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "3f299af22cc7ec7588e71f69c1f96d87a17fd94e", "submitter": { "id": 47154, "url": "http://patchwork.ozlabs.org/api/people/47154/?format=api", "name": "Chen-Yu Tsai", "email": "wens@csie.org" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170922072635.32105-4-wens@csie.org/mbox/", "series": [ { "id": 4550, "url": "http://patchwork.ozlabs.org/api/series/4550/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4550", "date": "2017-09-22T07:26:29", "name": "sunxi: A83T improvements", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4550/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817341/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817341/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xz4mh1Zmlz9sNc\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 17:26:58 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid DB50EC21FA6; Fri, 22 Sep 2017 07:26:48 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 77B04C21C29;\n\tFri, 22 Sep 2017 07:26:46 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 6116FC21E0E; Fri, 22 Sep 2017 07:26:44 +0000 (UTC)", "from wens.csie.org (mirror2.csie.ntu.edu.tw [140.112.30.76])\n\tby lists.denx.de (Postfix) with ESMTPS id 0545BC21C26\n\tfor <u-boot@lists.denx.de>; Fri, 22 Sep 2017 07:26:43 +0000 (UTC)", "by wens.csie.org (Postfix, from userid 1000)\n\tid B89B96002E; Fri, 22 Sep 2017 15:26:36 +0800 (CST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "Chen-Yu Tsai <wens@csie.org>", "To": "u-boot@lists.denx.de", "Date": "Fri, 22 Sep 2017 15:26:29 +0800", "Message-Id": "<20170922072635.32105-4-wens@csie.org>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170922072635.32105-1-wens@csie.org>", "References": "<20170922072635.32105-1-wens@csie.org>", "Cc": "Joe Hershberger <joe.hershberger@ni.com>, Jagan Teki <jagan@openedev.com>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>", "Subject": "[U-Boot] [PATCH 3/9] sunxi: Fix USB PHY control register offset for\n\tA83T", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "It was recently discovered that the USB PHY control register offset on\nthe A83T is 0x410 like on the A33, not 0x404. Fix it.\n\nFixes: 0c935acb9e5d (\"sunxi: usb_phy: Add support for A83T USB PHYs\")\nSigned-off-by: Chen-Yu Tsai <wens@csie.org>\n---\n arch/arm/mach-sunxi/usb_phy.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)", "diff": "diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c\nindex 9bf0b5633d4a..3fbef0050e3f 100644\n--- a/arch/arm/mach-sunxi/usb_phy.c\n+++ b/arch/arm/mach-sunxi/usb_phy.c\n@@ -19,7 +19,7 @@\n #include <errno.h>\n \n #define SUNXI_USB_PMU_IRQ_ENABLE\t0x800\n-#ifdef CONFIG_MACH_SUN8I_A33\n+#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T\n #define SUNXI_USB_CSR\t\t\t0x410\n #else\n #define SUNXI_USB_CSR\t\t\t0x404\n", "prefixes": [ "U-Boot", "3/9" ] }