[{"id":1773484,"web_url":"http://patchwork.ozlabs.org/comment/1773484/","msgid":"<20170922080544.arz6ztbizia6n74x@flea.lan>","list_archive_url":null,"date":"2017-09-22T08:05:44","subject":"Re: [U-Boot] [PATCH 3/9] sunxi: Fix USB PHY control register offset\n\tfor A83T","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi\n\nOn Fri, Sep 22, 2017 at 07:26:29AM +0000, Chen-Yu Tsai wrote:\n> It was recently discovered that the USB PHY control register offset on\n> the A83T is 0x410 like on the A33, not 0x404. Fix it.\n> \n> Fixes: 0c935acb9e5d (\"sunxi: usb_phy: Add support for A83T USB PHYs\")\n> Signed-off-by: Chen-Yu Tsai \n\nOk, so I think I screw this one up.\n\nI had already a patch for that that was queued by Jagan into another\nbranch.\n\nI've merged both branches, it should superseed this patch.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xz9mP2YCKz9sNw\n\tfor ;\n\tFri, 22 Sep 2017 21:12:05 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid BF133C21FAC; Fri, 22 Sep 2017 11:11:13 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DB934C21F88;\n\tFri, 22 Sep 2017 11:10:51 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid E373AC21C4A; Fri, 22 Sep 2017 11:10:49 +0000 (UTC)","from mail.free-electrons.com (mail.free-electrons.com [62.4.15.54])\n\tby lists.denx.de (Postfix) with ESMTP id 076E3C21C4A\n\tfor ; Fri, 22 Sep 2017 11:10:49 +0000 (UTC)","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 2C63920920; Fri, 22 Sep 2017 13:10:48 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id E0A4C208EF;\n\tFri, 22 Sep 2017 13:10:47 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.1 required=5.0 tests=DATE_IN_PAST_03_06\n\tautolearn=no autolearn_force=no version=3.4.0","Date":"Fri, 22 Sep 2017 10:05:44 +0200","From":"Maxime Ripard ","To":"Chen-Yu Tsai ","Message-ID":"<20170922080544.arz6ztbizia6n74x@flea.lan>","References":"<20170922072635.32105-1-wens@csie.org>\n\t<20170922072635.32105-4-wens@csie.org>","MIME-Version":"1.0","In-Reply-To":"<20170922072635.32105-4-wens@csie.org>","User-Agent":"NeoMutt/20170914 (1.9.0)","Cc":"u-boot@lists.denx.de, Jagan Teki ,\n\tJoe Hershberger ","Subject":"Re: [U-Boot] [PATCH 3/9] sunxi: Fix USB PHY control register offset\n\tfor A83T","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"multipart/mixed;\n\tboundary=\"===============0876161699617168185==\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]