| Message ID | 20170922072635.32105-4-wens@csie.org |
|---|---|
| State | Superseded |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | sunxi: A83T improvements | expand |
Hi On Fri, Sep 22, 2017 at 07:26:29AM +0000, Chen-Yu Tsai wrote: > It was recently discovered that the USB PHY control register offset on > the A83T is 0x410 like on the A33, not 0x404. Fix it. > > Fixes: 0c935acb9e5d ("sunxi: usb_phy: Add support for A83T USB PHYs") > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Ok, so I think I screw this one up. I had already a patch for that that was queued by Jagan into another branch. I've merged both branches, it should superseed this patch. Maxime
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 9bf0b5633d4a..3fbef0050e3f 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -19,7 +19,7 @@ #include <errno.h> #define SUNXI_USB_PMU_IRQ_ENABLE 0x800 -#ifdef CONFIG_MACH_SUN8I_A33 +#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T #define SUNXI_USB_CSR 0x410 #else #define SUNXI_USB_CSR 0x404
It was recently discovered that the USB PHY control register offset on the A83T is 0x410 like on the A33, not 0x404. Fix it. Fixes: 0c935acb9e5d ("sunxi: usb_phy: Add support for A83T USB PHYs") Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/mach-sunxi/usb_phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)