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GET /api/patches/815362/?format=api
{ "id": 815362, "url": "http://patchwork.ozlabs.org/api/patches/815362/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-7-git-send-email-chin.liang.see@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505812951-25088-7-git-send-email-chin.liang.see@intel.com>", "list_archive_url": null, "date": "2017-09-19T09:22:23", "name": "[U-Boot,06/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "212ea423b6cfc6ff428117d56f54573adcb1b145", "submitter": { "id": 70182, "url": "http://patchwork.ozlabs.org/api/people/70182/?format=api", "name": "See, Chin Liang", "email": "chin.liang.see@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-7-git-send-email-chin.liang.see@intel.com/mbox/", "series": [ { "id": 3810, "url": "http://patchwork.ozlabs.org/api/series/3810/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3810", "date": "2017-09-19T09:22:17", "name": "Enable Stratix10 SoC support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3810/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815362/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815362/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHbz1QzPz9s78\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 19:28:15 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid E0130C21EC6; Tue, 19 Sep 2017 09:25:40 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 17E35C21EF8;\n\tTue, 19 Sep 2017 09:23:45 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid F1AC2C21E00; Tue, 19 Sep 2017 09:23:34 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby lists.denx.de (Postfix) with ESMTPS id ED38BC21EC9\n\tfor <u-boot@lists.denx.de>; Tue, 19 Sep 2017 09:23:29 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:28 -0700", "from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:50 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220782268\"", "From": "chin.liang.see@intel.com", "To": "u-boot@lists.denx.de,\n\tMarek Vasut <marex@denx.de>", "Date": "Tue, 19 Sep 2017 17:22:23 +0800", "Message-Id": "<1505812951-25088-7-git-send-email-chin.liang.see@intel.com>", "X-Mailer": "git-send-email 2.2.2", "In-Reply-To": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "References": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "Cc": "Tien Fong Chee <tien.fong.chee@intel.com>,\n\tChin Liang See <chin.liang.see@intel.com>", "Subject": "[U-Boot] [PATCH 06/14] arm: socfpga: stratix10: Add misc support\n\tfor Stratix10 SoC", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Chin Liang See <chin.liang.see@intel.com>\n\nAdd misc support for Stratix SoC\n\nSigned-off-by: Chin Liang See <chin.liang.see@intel.com>\n---\n arch/arm/mach-socfpga/Makefile | 1 +\n arch/arm/mach-socfpga/misc.c | 4 +\n arch/arm/mach-socfpga/misc_s10.c | 165 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 170 insertions(+)\n create mode 100644 arch/arm/mach-socfpga/misc_s10.c", "diff": "diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\nindex 910eb6f..b253914 100644\n--- a/arch/arm/mach-socfpga/Makefile\n+++ b/arch/arm/mach-socfpga/Makefile\n@@ -32,6 +32,7 @@ endif\n \n ifdef CONFIG_TARGET_SOCFPGA_STRATIX10\n obj-y\t+= clock_manager_s10.o\n+obj-y\t+= misc_s10.o\n obj-y\t+= reset_manager_s10.o\n obj-y\t+= system_manager_s10.o\n obj-y\t+= wrap_pinmux_config_s10.o\ndiff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c\nindex 00eff90..2ea94bc 100644\n--- a/arch/arm/mach-socfpga/misc.c\n+++ b/arch/arm/mach-socfpga/misc.c\n@@ -23,8 +23,10 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n+#ifdef CONFIG_SYS_L2_PL310\n static const struct pl310_regs *const pl310 =\n \t(struct pl310_regs *)CONFIG_SYS_PL310_BASE;\n+#endif\n \n struct bsel bsel_str[] = {\n \t{ \"rsvd\", \"Reserved\", },\n@@ -53,6 +55,7 @@ void enable_caches(void)\n #endif\n }\n \n+#ifdef CONFIG_SYS_L2_PL310\n void v7_outer_cache_enable(void)\n {\n \t/* Disable the L2 cache */\n@@ -73,6 +76,7 @@ void v7_outer_cache_disable(void)\n \t/* Disable the L2 cache */\n \tclrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);\n }\n+#endif\n \n #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \\\n defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)\ndiff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c\nnew file mode 100644\nindex 0000000..b84f055\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/misc_s10.c\n@@ -0,0 +1,165 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0\n+ */\n+\n+#include <common.h>\n+#include <asm/io.h>\n+#include <errno.h>\n+#include <fdtdec.h>\n+#include <libfdt.h>\n+#include <altera.h>\n+#include <miiphy.h>\n+#include <netdev.h>\n+#include <watchdog.h>\n+#include <asm/arch/reset_manager.h>\n+#include <asm/arch/system_manager.h>\n+#include <asm/pl310.h>\n+\n+#include <dt-bindings/reset/altr,rst-mgr-s10.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static struct socfpga_system_manager *sysmgr_regs =\n+\t(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;\n+\n+/*\n+ * DesignWare Ethernet initialization\n+ */\n+#ifdef CONFIG_ETH_DESIGNWARE\n+void dwmac_deassert_reset(const unsigned int of_reset_id,\n+\t\t\t\t const u32 phymode)\n+{\n+\t/* Put the emac we're using into reset.\n+\t * This is required before configuring the PHY interface\n+\t */\n+\tsocfpga_emac_manage_reset(of_reset_id, 1);\n+\n+\tclrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),\n+\t\t\tSYSMGR_EMACGRP_CTRL_PHYSEL_MASK,\n+\t\t\tphymode);\n+\n+\tsocfpga_emac_manage_reset(of_reset_id, 0);\n+}\n+\n+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)\n+{\n+\tif (!phymode)\n+\t\treturn -EINVAL;\n+\n+\tif (!strcmp(phymode, \"mii\") || !strcmp(phymode, \"gmii\")) {\n+\t\t*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;\n+\t\treturn 0;\n+\t}\n+\n+\tif (!strcmp(phymode, \"rgmii\")) {\n+\t\t*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;\n+\t\treturn 0;\n+\t}\n+\n+\tif (!strcmp(phymode, \"rmii\")) {\n+\t\t*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int socfpga_eth_reset(void)\n+{\n+\tconst void *fdt = gd->fdt_blob;\n+\tstruct fdtdec_phandle_args args;\n+\tconst char *phy_mode;\n+\tu32 phy_modereg;\n+\tint nodes[2];\t/* Max. 3 GMACs */\n+\tint ret, count;\n+\tint i, node;\n+\n+\tcount = fdtdec_find_aliases_for_id(fdt, \"ethernet\",\n+\t\t\t\t\t COMPAT_ALTERA_SOCFPGA_DWMAC,\n+\t\t\t\t\t nodes, ARRAY_SIZE(nodes));\n+\tfor (i = 0; i < count; i++) {\n+\t\tnode = nodes[i];\n+\t\tif (node <= 0)\n+\t\t\tcontinue;\n+\n+\t\tret = fdtdec_parse_phandle_with_args(fdt, node, \"resets\",\n+\t\t\t\t\t\t \"#reset-cells\", 1, 0,\n+\t\t\t\t\t\t &args);\n+\t\tif (ret || (args.args_count != 1)) {\n+\t\t\tdebug(\"GMAC%i: Failed to parse DT 'resets'!\\n\", i);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tphy_mode = fdt_getprop(fdt, node, \"phy-mode\", NULL);\n+\t\tret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);\n+\t\tif (ret) {\n+\t\t\tdebug(\"GMAC%i: Failed to parse DT 'phy-mode'!\\n\", i);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tdwmac_deassert_reset(args.args[0], phy_modereg);\n+\t}\n+\n+\treturn 0;\n+}\n+#else\n+static int socfpga_eth_reset(void)\n+{\n+\treturn 0;\n+};\n+#endif\n+\n+/*\n+ * Print CPU information\n+ */\n+#if defined(CONFIG_DISPLAY_CPUINFO)\n+int print_cpuinfo(void)\n+{\n+\tputs(\"CPU: Intel FPGA SoCFPGA Platform\\n\");\n+\tputs(\"FPGA: Intel FPGA Stratix 10\\n\");\n+\treturn 0;\n+}\n+#endif\n+\n+#ifdef CONFIG_ARCH_MISC_INIT\n+int arch_misc_init(void)\n+{\n+\treturn socfpga_eth_reset();\n+}\n+#endif\n+\n+int arch_early_init_r(void)\n+{\n+\treturn 0;\n+}\n+\n+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])\n+{\n+\tif (argc != 2)\n+\t\treturn CMD_RET_USAGE;\n+\n+\targv++;\n+\n+\tswitch (*argv[0]) {\n+\tcase 'e':\t/* Enable */\n+\t\tsocfpga_bridges_reset(1);\n+\t\tbreak;\n+\tcase 'd':\t/* Disable */\n+\t\tsocfpga_bridges_reset(0);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn CMD_RET_USAGE;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_CMD(\n+\tbridge, 2, 1, do_bridge,\n+\t\"SoCFPGA HPS FPGA bridge control\",\n+\t\"enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\\n\"\n+\t\"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\\n\"\n+\t\"\"\n+);\n", "prefixes": [ "U-Boot", "06/14" ] }