| Message ID | 1505812951-25088-7-git-send-email-chin.liang.see@intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Enable Stratix10 SoC support | expand |
On Tue, Sep 19, 2017 at 4:22 AM, <chin.liang.see@intel.com> wrote: > From: Chin Liang See <chin.liang.see@intel.com> > > Add misc support for Stratix SoC Just because the file is call misc.c doesn't mean you can just keep the commit message that simple. Can you add what functions are you adding? > > Signed-off-by: Chin Liang See <chin.liang.see@intel.com> > --- > arch/arm/mach-socfpga/Makefile | 1 + > arch/arm/mach-socfpga/misc.c | 4 + > arch/arm/mach-socfpga/misc_s10.c | 165 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 170 insertions(+) > create mode 100644 arch/arm/mach-socfpga/misc_s10.c > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > index 910eb6f..b253914 100644 > --- a/arch/arm/mach-socfpga/Makefile > +++ b/arch/arm/mach-socfpga/Makefile > @@ -32,6 +32,7 @@ endif > > ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 > obj-y += clock_manager_s10.o > +obj-y += misc_s10.o > obj-y += reset_manager_s10.o > obj-y += system_manager_s10.o > obj-y += wrap_pinmux_config_s10.o > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c > index 00eff90..2ea94bc 100644 > --- a/arch/arm/mach-socfpga/misc.c > +++ b/arch/arm/mach-socfpga/misc.c > @@ -23,8 +23,10 @@ > > DECLARE_GLOBAL_DATA_PTR; > > +#ifdef CONFIG_SYS_L2_PL310 > static const struct pl310_regs *const pl310 = > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > +#endif > > struct bsel bsel_str[] = { > { "rsvd", "Reserved", }, > @@ -53,6 +55,7 @@ void enable_caches(void) > #endif > } > > +#ifdef CONFIG_SYS_L2_PL310 > void v7_outer_cache_enable(void) > { > /* Disable the L2 cache */ > @@ -73,6 +76,7 @@ void v7_outer_cache_disable(void) > /* Disable the L2 cache */ > clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > } > +#endif > > #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ > defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) > diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c > new file mode 100644 > index 0000000..b84f055 > --- /dev/null > +++ b/arch/arm/mach-socfpga/misc_s10.c This misc_s10.c look very similar to the Gen5 stuff, can you re-use it? Dinh
On Tue, 2017-09-26 at 17:46 -0500, Dinh Nguyen wrote: > On Tue, Sep 19, 2017 at 4:22 AM, <chin.liang.see@intel.com> wrote: > > > > From: Chin Liang See <chin.liang.see@intel.com> > > > > Add misc support for Stratix SoC > Just because the file is call misc.c doesn't mean you can just keep > the commit > message that simple. Can you add what functions are you adding? > Definitely can add more details here > > > > > > Signed-off-by: Chin Liang See <chin.liang.see@intel.com> > > --- > > arch/arm/mach-socfpga/Makefile | 1 + > > arch/arm/mach-socfpga/misc.c | 4 + > > arch/arm/mach-socfpga/misc_s10.c | 165 > > +++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 170 insertions(+) > > create mode 100644 arch/arm/mach-socfpga/misc_s10.c > > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach- > > socfpga/Makefile > > index 910eb6f..b253914 100644 > > --- a/arch/arm/mach-socfpga/Makefile > > +++ b/arch/arm/mach-socfpga/Makefile > > @@ -32,6 +32,7 @@ endif > > > > ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 > > obj-y += clock_manager_s10.o > > +obj-y += misc_s10.o > > obj-y += reset_manager_s10.o > > obj-y += system_manager_s10.o > > obj-y += wrap_pinmux_config_s10.o > > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach- > > socfpga/misc.c > > index 00eff90..2ea94bc 100644 > > --- a/arch/arm/mach-socfpga/misc.c > > +++ b/arch/arm/mach-socfpga/misc.c > > @@ -23,8 +23,10 @@ > > > > DECLARE_GLOBAL_DATA_PTR; > > > > +#ifdef CONFIG_SYS_L2_PL310 > > static const struct pl310_regs *const pl310 = > > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > > +#endif > > > > struct bsel bsel_str[] = { > > { "rsvd", "Reserved", }, > > @@ -53,6 +55,7 @@ void enable_caches(void) > > #endif > > } > > > > +#ifdef CONFIG_SYS_L2_PL310 > > void v7_outer_cache_enable(void) > > { > > /* Disable the L2 cache */ > > @@ -73,6 +76,7 @@ void v7_outer_cache_disable(void) > > /* Disable the L2 cache */ > > clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > > } > > +#endif > > > > #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ > > defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) > > diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach- > > socfpga/misc_s10.c > > new file mode 100644 > > index 0000000..b84f055 > > --- /dev/null > > +++ b/arch/arm/mach-socfpga/misc_s10.c > This misc_s10.c look very similar to the Gen5 stuff, can you re-use > it? Yes, its true. Let me move eth stuff to common. Chin Liang > > Dinh
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 910eb6f..b253914 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -32,6 +32,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += misc_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += wrap_pinmux_config_s10.o diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 00eff90..2ea94bc 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -23,8 +23,10 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +#endif struct bsel bsel_str[] = { { "rsvd", "Reserved", }, @@ -53,6 +55,7 @@ void enable_caches(void) #endif } +#ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { /* Disable the L2 cache */ @@ -73,6 +76,7 @@ void v7_outer_cache_disable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } +#endif #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c new file mode 100644 index 0000000..b84f055 --- /dev/null +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <altera.h> +#include <miiphy.h> +#include <netdev.h> +#include <watchdog.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/pl310.h> + +#include <dt-bindings/reset/altr,rst-mgr-s10.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_ETH_DESIGNWARE +void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) +{ + /* Put the emac we're using into reset. + * This is required before configuring the PHY interface + */ + socfpga_emac_manage_reset(of_reset_id, 1); + + clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET), + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + phymode); + + socfpga_emac_manage_reset(of_reset_id, 0); +} + +static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) +{ + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + return 0; + } + + if (!strcmp(phymode, "rgmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + return 0; + } + + if (!strcmp(phymode, "rmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + return 0; + } + + return -EINVAL; +} + +static int socfpga_eth_reset(void) +{ + const void *fdt = gd->fdt_blob; + struct fdtdec_phandle_args args; + const char *phy_mode; + u32 phy_modereg; + int nodes[2]; /* Max. 3 GMACs */ + int ret, count; + int i, node; + + count = fdtdec_find_aliases_for_id(fdt, "ethernet", + COMPAT_ALTERA_SOCFPGA_DWMAC, + nodes, ARRAY_SIZE(nodes)); + for (i = 0; i < count; i++) { + node = nodes[i]; + if (node <= 0) + continue; + + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", + "#reset-cells", 1, 0, + &args); + if (ret || (args.args_count != 1)) { + debug("GMAC%i: Failed to parse DT 'resets'!\n", i); + continue; + } + + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + + dwmac_deassert_reset(args.args[0], phy_modereg); + } + + return 0; +} +#else +static int socfpga_eth_reset(void) +{ + return 0; +}; +#endif + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + puts("CPU: Intel FPGA SoCFPGA Platform\n"); + puts("FPGA: Intel FPGA Stratix 10\n"); + return 0; +} +#endif + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + return socfpga_eth_reset(); +} +#endif + +int arch_early_init_r(void) +{ + return 0; +} + +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + argv++; + + switch (*argv[0]) { + case 'e': /* Enable */ + socfpga_bridges_reset(1); + break; + case 'd': /* Disable */ + socfpga_bridges_reset(0); + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" +);