Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/812722/?format=api
{ "id": 812722, "url": "http://patchwork.ozlabs.org/api/patches/812722/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/1505205277-26276-4-git-send-email-charles.baylis@linaro.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505205277-26276-4-git-send-email-charles.baylis@linaro.org>", "list_archive_url": null, "date": "2017-09-12T08:34:37", "name": "[3/3,ARM] Add table of costs for AAarch32 addressing modes.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a32dc8f5d3db1b6b54d19f17fa32b0ea3ed9bcd6", "submitter": { "id": 35578, "url": "http://patchwork.ozlabs.org/api/people/35578/?format=api", "name": "Charles Baylis", "email": "charles.baylis@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/1505205277-26276-4-git-send-email-charles.baylis@linaro.org/mbox/", "series": [ { "id": 2631, "url": "http://patchwork.ozlabs.org/api/series/2631/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=2631", "date": "2017-09-12T08:34:34", "name": "Addressing mode costs v3", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2631/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812722/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812722/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461895-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461895-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"ROENoLY8\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrymt2Wxhz9s7g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 12 Sep 2017 18:35:58 +1000 (AEST)", "(qmail 76493 invoked by alias); 12 Sep 2017 08:35:04 -0000", "(qmail 76399 invoked by uid 89); 12 Sep 2017 08:35:03 -0000", "from mail-wr0-f182.google.com (HELO mail-wr0-f182.google.com)\n\t(209.85.128.182) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 12 Sep 2017 08:35:01 +0000", "by mail-wr0-f182.google.com with SMTP id 108so19040632wra.5 for\n\t<gcc-patches@gcc.gnu.org>; Tue, 12 Sep 2017 01:35:00 -0700 (PDT)", "from localhost.localdomain\n\t(cpc92322-cmbg19-2-0-cust1928.5-4.cable.virginm.net.\n\t[86.26.39.137]) by smtp.gmail.com with ESMTPSA id\n\ts126sm13321227wmd.46.2017.09.12.01.34.58 (version=TLS1_2\n\tcipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 12 Sep 2017 01:34:58 -0700 (PDT)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:cc:subject:date:message-id:in-reply-to:references; q=dns; s=\n\tdefault; b=JVQKP6rPpZwseOLDjEb8twAL+99m9tTj9/tPUViAc65qEc4fyatpz\n\t42p+KElWKSlkFdUB9vp3yU8HjW+OtHoLeJ5v/1ONVysSt7Hn/4GFcrvCofYYDTsf\n\tfiWQf1udeN5LKvjEjwVpQii6LmLd5QcNp22bgcWVhpkDLoXmMQFP1c=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:cc:subject:date:message-id:in-reply-to:references; s=\n\tdefault; bh=wYebF4JJBs07OMEN24wCwcpy7ww=; b=ROENoLY8sBg2nocGGxWI\n\ttk4uWwH3trJw9G75AdNFvrbmsuH3Nt0vS0KPXhqbc1LKQ2iWelFteZV9oyPPXqJC\n\tCGf1b1LSpf5YIHxIKleCPyFpteLXYEwWG9L6PA0DJyN83OAuR0KIP2tovQQpbPMt\n\tqfVClcSobkw/N0ZTpDn6+1o=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-25.0 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "mail-wr0-f182.google.com", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references; bh=NbPr68XWvqbEmdxyvktwj0aLFXIp7UXh/gXRQgvwtaY=;\n\tb=QaobSZFPuEfmhdCKOOEB094iIuR8haZ0gsgGhGrLmgL/mUFSwR3y9wRGht5YFKoYx2\n\tLKAImAWjKFWUHLAOOAfMx0hbzQNQmCFSfk4mMwP1iExNOTexAX53GdbjNWsjFRYGO1NF\n\tZot2N0NmB6ISbJS3X8EUpnsow0LlBv2PaInqC2HSfo5DGBznnxbm0UJpCvM8Cr0JWs9j\n\tjQ17lHSCcWESSrdOVxSWDo3qbCRIlDI7/8RdzpOqBhn8l1L5X8PMob0SwKtkS64hE8y8\n\tsvs32h1GYPW2LhMnsc9babBRqGYRhAFnrOnWQphGF66gzdmNsnb3Af2b+7+2dLEYBbE2\n\tzfpw==", "X-Gm-Message-State": "AHPjjUgOszRQq1NWvfDs1g7cVELEjIadG6Ty/exuWT+DlXj9h9JF7763\tgFixgQ/MJIBjiPNh", "X-Google-Smtp-Source": "ADKCNb7g5sYK9THP5SxObAdvrsheT099B9u+vL9VL8x20ks1GGKOWnMdLI67cG652sTb9Oq2R7dL1w==", "X-Received": "by 10.223.134.157 with SMTP id 29mr10310783wrx.72.1505205299180;\n\tTue, 12 Sep 2017 01:34:59 -0700 (PDT)", "From": "charles.baylis@linaro.org", "To": "rearnsha@arm.com, Ramana.Radhakrishnan@arm.com, pinskia@gmail.com,\n\tkyrylo.tkachov@arm.com", "Cc": "gcc-patches@gcc.gnu.org", "Subject": "[PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing modes.", "Date": "Tue, 12 Sep 2017 09:34:37 +0100", "Message-Id": "<1505205277-26276-4-git-send-email-charles.baylis@linaro.org>", "In-Reply-To": "<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>", "References": "<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>", "X-IsSubscribed": "yes" }, "content": "From: Charles Baylis <charles.baylis@linaro.org>\n\nThis patch adds support for modelling the varying costs of\ndifferent addressing modes. The generic cost table treats\nall addressing modes as having equal cost.\n\ngcc/ChangeLog:\n\n<date> Charles Baylis <charles.baylis@linaro.org>\n\n\t* config/arm/arm-protos.h (enum arm_addr_mode_op): New.\n\t(struct addr_mode_cost_table): New.\n\t(struct tune_params): Add field addr_mode_costs.\n\t* config/arm/arm.c (generic_addr_mode_costs): New.\n\t(arm_slowmul_tune): Initialise addr_mode_costs field.\n\t(arm_fastmul_tune): Likewise.\n\t(arm_strongarm_tune): Likewise.\n\t(arm_xscale_tune): Likewise.\n\t(arm_9e_tune): Likewise.\n\t(arm_marvell_pj4_tune): Likewise.\n\t(arm_v6t2_tune): Likewise.\n\t(arm_cortex_tune): Likewise.\n\t(arm_cortex_a8_tune): Likewise.\n\t(arm_cortex_a7_tune): Likewise.\n\t(arm_cortex_a15_tune): Likewise.\n\t(arm_cortex_a35_tune): Likewise.\n\t(arm_cortex_a53_tune): Likewise.\n\t(arm_cortex_a57_tune): Likewise.\n\t(arm_exynosm1_tune): Likewise.\n\t(arm_xgene1_tune): Likewise.\n\t(arm_cortex_a5_tune): Likewise.\n\t(arm_cortex_a9_tune): Likewise.\n\t(arm_cortex_a12_tune): Likewise.\n\t(arm_cortex_a73_tune): Likewise.\n\t(arm_v7m_tune): Likewise.\n\t(arm_cortex_m7_tune): Likewise.\n\t(arm_v6m_tune): Likewise.\n\t(arm_fa726te_tune): Likewise.\n\t(arm_mem_costs): Use table lookup to calculate cost of addressing\n\tmode.\n\nChange-Id: If71bd7c4f4bb876c5ed82dc28791130efb8bf89e\n---\n gcc/config/arm/arm-protos.h | 20 +++++++++++\n gcc/config/arm/arm.c | 83 ++++++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 102 insertions(+), 1 deletion(-)", "diff": "diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h\nindex 47a85cc..3d6b515 100644\n--- a/gcc/config/arm/arm-protos.h\n+++ b/gcc/config/arm/arm-protos.h\n@@ -261,12 +261,32 @@ struct cpu_vec_costs {\n \n struct cpu_cost_table;\n \n+/* Addressing mode operations. Used to index tables in struct\n+ addr_mode_cost_table. */\n+enum arm_addr_mode_op\n+{\n+ AMO_DEFAULT,\n+ AMO_NO_WB,\t/* Offset with no writeback. */\n+ AMO_WB,\t/* Offset with writeback. */\n+ AMO_MAX\t/* For array size. */\n+};\n+\n+/* Table of additional costs when using addressing modes for each\n+ access type. */\n+struct addr_mode_cost_table\n+{\n+ const int integer[AMO_MAX];\n+ const int fp[AMO_MAX];\n+ const int vector[AMO_MAX];\n+};\n+\n /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this\n structure is modified. */\n \n struct tune_params\n {\n const struct cpu_cost_table *insn_extra_cost;\n+ const struct addr_mode_cost_table *addr_mode_costs;\n bool (*sched_adjust_cost) (rtx_insn *, int, rtx_insn *, int *);\n int (*branch_cost) (bool, bool);\n /* Vectorizer costs. */\ndiff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\nindex b8dbed6..0d31f5f 100644\n--- a/gcc/config/arm/arm.c\n+++ b/gcc/config/arm/arm.c\n@@ -1751,9 +1751,32 @@ const struct cpu_cost_table v7m_extra_costs =\n }\n };\n \n+const struct addr_mode_cost_table generic_addr_mode_costs =\n+{\n+ /* int. */\n+ {\n+ 0, /* AMO_DEFAULT. */\n+ 0, /* AMO_NO_WB. */\n+ 0 /* AMO_WB. */\n+ },\n+ /* float. */\n+ {\n+ 0, /* AMO_DEFAULT. */\n+ 0, /* AMO_NO_WB. */\n+ 0 /* AMO_WB. */\n+ },\n+ /* vector. */\n+ {\n+ 0, /* AMO_DEFAULT. */\n+ 0, /* AMO_NO_WB. */\n+ 0 /* AMO_WB. */\n+ }\n+};\n+\n const struct tune_params arm_slowmul_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1777,6 +1800,7 @@ const struct tune_params arm_slowmul_tune =\n const struct tune_params arm_fastmul_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1803,6 +1827,7 @@ const struct tune_params arm_fastmul_tune =\n const struct tune_params arm_strongarm_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1826,6 +1851,7 @@ const struct tune_params arm_strongarm_tune =\n const struct tune_params arm_xscale_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n xscale_sched_adjust_cost,\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1849,6 +1875,7 @@ const struct tune_params arm_xscale_tune =\n const struct tune_params arm_9e_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1872,6 +1899,7 @@ const struct tune_params arm_9e_tune =\n const struct tune_params arm_marvell_pj4_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1895,6 +1923,7 @@ const struct tune_params arm_marvell_pj4_tune =\n const struct tune_params arm_v6t2_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1920,6 +1949,7 @@ const struct tune_params arm_v6t2_tune =\n const struct tune_params arm_cortex_tune =\n {\n &generic_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1943,6 +1973,7 @@ const struct tune_params arm_cortex_tune =\n const struct tune_params arm_cortex_a8_tune =\n {\n &cortexa8_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1966,6 +1997,7 @@ const struct tune_params arm_cortex_a8_tune =\n const struct tune_params arm_cortex_a7_tune =\n {\n &cortexa7_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1989,6 +2021,7 @@ const struct tune_params arm_cortex_a7_tune =\n const struct tune_params arm_cortex_a15_tune =\n {\n &cortexa15_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2012,6 +2045,7 @@ const struct tune_params arm_cortex_a15_tune =\n const struct tune_params arm_cortex_a35_tune =\n {\n &cortexa53_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2035,6 +2069,7 @@ const struct tune_params arm_cortex_a35_tune =\n const struct tune_params arm_cortex_a53_tune =\n {\n &cortexa53_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2058,6 +2093,7 @@ const struct tune_params arm_cortex_a53_tune =\n const struct tune_params arm_cortex_a57_tune =\n {\n &cortexa57_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* addressing mode costs */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2081,6 +2117,7 @@ const struct tune_params arm_cortex_a57_tune =\n const struct tune_params arm_exynosm1_tune =\n {\n &exynosm1_extra_costs,\n+ &generic_addr_mode_costs,\t\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2104,6 +2141,7 @@ const struct tune_params arm_exynosm1_tune =\n const struct tune_params arm_xgene1_tune =\n {\n &xgene1_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2130,6 +2168,7 @@ const struct tune_params arm_xgene1_tune =\n const struct tune_params arm_cortex_a5_tune =\n {\n &cortexa5_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_cortex_a5_branch_cost,\n &arm_default_vec_cost,\n@@ -2153,6 +2192,7 @@ const struct tune_params arm_cortex_a5_tune =\n const struct tune_params arm_cortex_a9_tune =\n {\n &cortexa9_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n cortex_a9_sched_adjust_cost,\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2176,6 +2216,7 @@ const struct tune_params arm_cortex_a9_tune =\n const struct tune_params arm_cortex_a12_tune =\n {\n &cortexa12_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost, /* Vectorizer costs. */\n@@ -2199,6 +2240,7 @@ const struct tune_params arm_cortex_a12_tune =\n const struct tune_params arm_cortex_a73_tune =\n {\n &cortexa57_extra_costs,\n+ &generic_addr_mode_costs,\t\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\t\t\t/* Vectorizer costs. */\n@@ -2229,6 +2271,7 @@ const struct tune_params arm_cortex_a73_tune =\n const struct tune_params arm_v7m_tune =\n {\n &v7m_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_cortex_m_branch_cost,\n &arm_default_vec_cost,\n@@ -2254,6 +2297,7 @@ const struct tune_params arm_v7m_tune =\n const struct tune_params arm_cortex_m7_tune =\n {\n &v7m_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_cortex_m7_branch_cost,\n &arm_default_vec_cost,\n@@ -2280,6 +2324,7 @@ const struct tune_params arm_cortex_m7_tune =\n const struct tune_params arm_v6m_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost, /* Vectorizer costs. */\n@@ -2303,6 +2348,7 @@ const struct tune_params arm_v6m_tune =\n const struct tune_params arm_fa726te_tune =\n {\n &generic_extra_costs,\t\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t\t/* Addressing mode costs. */\n fa726te_sched_adjust_cost,\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -9249,7 +9295,42 @@ arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost,\n /* Calculate cost of the addressing mode. */\n if (speed_p)\n {\n- /* TODO: Add table-driven costs for addressing modes. (See patch 2) */\n+ arm_addr_mode_op op_type;\n+ switch (GET_CODE (XEXP (x, 0)))\n+\t{\n+\tdefault:\n+\tcase REG:\n+\t op_type = AMO_DEFAULT;\n+\t break;\n+\tcase MINUS:\n+\t /* MINUS does not appear in RTL, but the architecture supports it,\n+\t so handle this case defensively. */\n+\t /* fall through */\n+\tcase PLUS:\n+\t op_type = AMO_NO_WB;\n+\t break;\n+\tcase PRE_INC:\n+\tcase PRE_DEC:\n+\tcase POST_INC:\n+\tcase POST_DEC:\n+\tcase PRE_MODIFY:\n+\tcase POST_MODIFY:\n+\t op_type = AMO_WB;\n+\t break;\n+\t}\n+\n+ if (VECTOR_MODE_P (mode))\n+\t{\n+\t *cost += current_tune->addr_mode_costs->vector[op_type];\n+\t}\n+ else if (FLOAT_MODE_P (mode))\n+\t{\n+\t *cost += current_tune->addr_mode_costs->fp[op_type];\n+\t}\n+ else\n+\t{\n+\t *cost += current_tune->addr_mode_costs->integer[op_type];\n+\t}\n }\n \n /* Calculate cost of memory access. */\n", "prefixes": [ "3/3", "ARM" ] }