From patchwork Tue Sep 12 08:34:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Baylis X-Patchwork-Id: 812722 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-461895-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ROENoLY8"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xrymt2Wxhz9s7g for ; Tue, 12 Sep 2017 18:35:58 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=JVQKP6rPpZwseOLDjEb8twAL+99m9tTj9/tPUViAc65qEc4fyatpz 42p+KElWKSlkFdUB9vp3yU8HjW+OtHoLeJ5v/1ONVysSt7Hn/4GFcrvCofYYDTsf fiWQf1udeN5LKvjEjwVpQii6LmLd5QcNp22bgcWVhpkDLoXmMQFP1c= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=wYebF4JJBs07OMEN24wCwcpy7ww=; b=ROENoLY8sBg2nocGGxWI tk4uWwH3trJw9G75AdNFvrbmsuH3Nt0vS0KPXhqbc1LKQ2iWelFteZV9oyPPXqJC CGf1b1LSpf5YIHxIKleCPyFpteLXYEwWG9L6PA0DJyN83OAuR0KIP2tovQQpbPMt qfVClcSobkw/N0ZTpDn6+1o= Received: (qmail 76493 invoked by alias); 12 Sep 2017 08:35:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 76399 invoked by uid 89); 12 Sep 2017 08:35:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wr0-f182.google.com Received: from mail-wr0-f182.google.com (HELO mail-wr0-f182.google.com) (209.85.128.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Sep 2017 08:35:01 +0000 Received: by mail-wr0-f182.google.com with SMTP id 108so19040632wra.5 for ; Tue, 12 Sep 2017 01:35:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NbPr68XWvqbEmdxyvktwj0aLFXIp7UXh/gXRQgvwtaY=; b=QaobSZFPuEfmhdCKOOEB094iIuR8haZ0gsgGhGrLmgL/mUFSwR3y9wRGht5YFKoYx2 LKAImAWjKFWUHLAOOAfMx0hbzQNQmCFSfk4mMwP1iExNOTexAX53GdbjNWsjFRYGO1NF Zot2N0NmB6ISbJS3X8EUpnsow0LlBv2PaInqC2HSfo5DGBznnxbm0UJpCvM8Cr0JWs9j jQ17lHSCcWESSrdOVxSWDo3qbCRIlDI7/8RdzpOqBhn8l1L5X8PMob0SwKtkS64hE8y8 svs32h1GYPW2LhMnsc9babBRqGYRhAFnrOnWQphGF66gzdmNsnb3Af2b+7+2dLEYBbE2 zfpw== X-Gm-Message-State: AHPjjUgOszRQq1NWvfDs1g7cVELEjIadG6Ty/exuWT+DlXj9h9JF7763 gFixgQ/MJIBjiPNh X-Google-Smtp-Source: ADKCNb7g5sYK9THP5SxObAdvrsheT099B9u+vL9VL8x20ks1GGKOWnMdLI67cG652sTb9Oq2R7dL1w== X-Received: by 10.223.134.157 with SMTP id 29mr10310783wrx.72.1505205299180; Tue, 12 Sep 2017 01:34:59 -0700 (PDT) Received: from localhost.localdomain (cpc92322-cmbg19-2-0-cust1928.5-4.cable.virginm.net. [86.26.39.137]) by smtp.gmail.com with ESMTPSA id s126sm13321227wmd.46.2017.09.12.01.34.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Sep 2017 01:34:58 -0700 (PDT) From: charles.baylis@linaro.org To: rearnsha@arm.com, Ramana.Radhakrishnan@arm.com, pinskia@gmail.com, kyrylo.tkachov@arm.com Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing modes. Date: Tue, 12 Sep 2017 09:34:37 +0100 Message-Id: <1505205277-26276-4-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> References: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes From: Charles Baylis This patch adds support for modelling the varying costs of different addressing modes. The generic cost table treats all addressing modes as having equal cost. gcc/ChangeLog: Charles Baylis * config/arm/arm-protos.h (enum arm_addr_mode_op): New. (struct addr_mode_cost_table): New. (struct tune_params): Add field addr_mode_costs. * config/arm/arm.c (generic_addr_mode_costs): New. (arm_slowmul_tune): Initialise addr_mode_costs field. (arm_fastmul_tune): Likewise. (arm_strongarm_tune): Likewise. (arm_xscale_tune): Likewise. (arm_9e_tune): Likewise. (arm_marvell_pj4_tune): Likewise. (arm_v6t2_tune): Likewise. (arm_cortex_tune): Likewise. (arm_cortex_a8_tune): Likewise. (arm_cortex_a7_tune): Likewise. (arm_cortex_a15_tune): Likewise. (arm_cortex_a35_tune): Likewise. (arm_cortex_a53_tune): Likewise. (arm_cortex_a57_tune): Likewise. (arm_exynosm1_tune): Likewise. (arm_xgene1_tune): Likewise. (arm_cortex_a5_tune): Likewise. (arm_cortex_a9_tune): Likewise. (arm_cortex_a12_tune): Likewise. (arm_cortex_a73_tune): Likewise. (arm_v7m_tune): Likewise. (arm_cortex_m7_tune): Likewise. (arm_v6m_tune): Likewise. (arm_fa726te_tune): Likewise. (arm_mem_costs): Use table lookup to calculate cost of addressing mode. Change-Id: If71bd7c4f4bb876c5ed82dc28791130efb8bf89e --- gcc/config/arm/arm-protos.h | 20 +++++++++++ gcc/config/arm/arm.c | 83 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 47a85cc..3d6b515 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -261,12 +261,32 @@ struct cpu_vec_costs { struct cpu_cost_table; +/* Addressing mode operations. Used to index tables in struct + addr_mode_cost_table. */ +enum arm_addr_mode_op +{ + AMO_DEFAULT, + AMO_NO_WB, /* Offset with no writeback. */ + AMO_WB, /* Offset with writeback. */ + AMO_MAX /* For array size. */ +}; + +/* Table of additional costs when using addressing modes for each + access type. */ +struct addr_mode_cost_table +{ + const int integer[AMO_MAX]; + const int fp[AMO_MAX]; + const int vector[AMO_MAX]; +}; + /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this structure is modified. */ struct tune_params { const struct cpu_cost_table *insn_extra_cost; + const struct addr_mode_cost_table *addr_mode_costs; bool (*sched_adjust_cost) (rtx_insn *, int, rtx_insn *, int *); int (*branch_cost) (bool, bool); /* Vectorizer costs. */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b8dbed6..0d31f5f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1751,9 +1751,32 @@ const struct cpu_cost_table v7m_extra_costs = } }; +const struct addr_mode_cost_table generic_addr_mode_costs = +{ + /* int. */ + { + 0, /* AMO_DEFAULT. */ + 0, /* AMO_NO_WB. */ + 0 /* AMO_WB. */ + }, + /* float. */ + { + 0, /* AMO_DEFAULT. */ + 0, /* AMO_NO_WB. */ + 0 /* AMO_WB. */ + }, + /* vector. */ + { + 0, /* AMO_DEFAULT. */ + 0, /* AMO_NO_WB. */ + 0 /* AMO_WB. */ + } +}; + const struct tune_params arm_slowmul_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1777,6 +1800,7 @@ const struct tune_params arm_slowmul_tune = const struct tune_params arm_fastmul_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1803,6 +1827,7 @@ const struct tune_params arm_fastmul_tune = const struct tune_params arm_strongarm_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1826,6 +1851,7 @@ const struct tune_params arm_strongarm_tune = const struct tune_params arm_xscale_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ xscale_sched_adjust_cost, arm_default_branch_cost, &arm_default_vec_cost, @@ -1849,6 +1875,7 @@ const struct tune_params arm_xscale_tune = const struct tune_params arm_9e_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1872,6 +1899,7 @@ const struct tune_params arm_9e_tune = const struct tune_params arm_marvell_pj4_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1895,6 +1923,7 @@ const struct tune_params arm_marvell_pj4_tune = const struct tune_params arm_v6t2_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1920,6 +1949,7 @@ const struct tune_params arm_v6t2_tune = const struct tune_params arm_cortex_tune = { &generic_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1943,6 +1973,7 @@ const struct tune_params arm_cortex_tune = const struct tune_params arm_cortex_a8_tune = { &cortexa8_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1966,6 +1997,7 @@ const struct tune_params arm_cortex_a8_tune = const struct tune_params arm_cortex_a7_tune = { &cortexa7_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1989,6 +2021,7 @@ const struct tune_params arm_cortex_a7_tune = const struct tune_params arm_cortex_a15_tune = { &cortexa15_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2012,6 +2045,7 @@ const struct tune_params arm_cortex_a15_tune = const struct tune_params arm_cortex_a35_tune = { &cortexa53_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2035,6 +2069,7 @@ const struct tune_params arm_cortex_a35_tune = const struct tune_params arm_cortex_a53_tune = { &cortexa53_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2058,6 +2093,7 @@ const struct tune_params arm_cortex_a53_tune = const struct tune_params arm_cortex_a57_tune = { &cortexa57_extra_costs, + &generic_addr_mode_costs, /* addressing mode costs */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2081,6 +2117,7 @@ const struct tune_params arm_cortex_a57_tune = const struct tune_params arm_exynosm1_tune = { &exynosm1_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2104,6 +2141,7 @@ const struct tune_params arm_exynosm1_tune = const struct tune_params arm_xgene1_tune = { &xgene1_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2130,6 +2168,7 @@ const struct tune_params arm_xgene1_tune = const struct tune_params arm_cortex_a5_tune = { &cortexa5_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_cortex_a5_branch_cost, &arm_default_vec_cost, @@ -2153,6 +2192,7 @@ const struct tune_params arm_cortex_a5_tune = const struct tune_params arm_cortex_a9_tune = { &cortexa9_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ cortex_a9_sched_adjust_cost, arm_default_branch_cost, &arm_default_vec_cost, @@ -2176,6 +2216,7 @@ const struct tune_params arm_cortex_a9_tune = const struct tune_params arm_cortex_a12_tune = { &cortexa12_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, /* Vectorizer costs. */ @@ -2199,6 +2240,7 @@ const struct tune_params arm_cortex_a12_tune = const struct tune_params arm_cortex_a73_tune = { &cortexa57_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, /* Vectorizer costs. */ @@ -2229,6 +2271,7 @@ const struct tune_params arm_cortex_a73_tune = const struct tune_params arm_v7m_tune = { &v7m_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_cortex_m_branch_cost, &arm_default_vec_cost, @@ -2254,6 +2297,7 @@ const struct tune_params arm_v7m_tune = const struct tune_params arm_cortex_m7_tune = { &v7m_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_cortex_m7_branch_cost, &arm_default_vec_cost, @@ -2280,6 +2324,7 @@ const struct tune_params arm_cortex_m7_tune = const struct tune_params arm_v6m_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, /* Vectorizer costs. */ @@ -2303,6 +2348,7 @@ const struct tune_params arm_v6m_tune = const struct tune_params arm_fa726te_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ fa726te_sched_adjust_cost, arm_default_branch_cost, &arm_default_vec_cost, @@ -9249,7 +9295,42 @@ arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost, /* Calculate cost of the addressing mode. */ if (speed_p) { - /* TODO: Add table-driven costs for addressing modes. (See patch 2) */ + arm_addr_mode_op op_type; + switch (GET_CODE (XEXP (x, 0))) + { + default: + case REG: + op_type = AMO_DEFAULT; + break; + case MINUS: + /* MINUS does not appear in RTL, but the architecture supports it, + so handle this case defensively. */ + /* fall through */ + case PLUS: + op_type = AMO_NO_WB; + break; + case PRE_INC: + case PRE_DEC: + case POST_INC: + case POST_DEC: + case PRE_MODIFY: + case POST_MODIFY: + op_type = AMO_WB; + break; + } + + if (VECTOR_MODE_P (mode)) + { + *cost += current_tune->addr_mode_costs->vector[op_type]; + } + else if (FLOAT_MODE_P (mode)) + { + *cost += current_tune->addr_mode_costs->fp[op_type]; + } + else + { + *cost += current_tune->addr_mode_costs->integer[op_type]; + } } /* Calculate cost of memory access. */