[{"id":1767690,"web_url":"http://patchwork.ozlabs.org/comment/1767690/","msgid":"<59B8F435.7000706@foss.arm.com>","list_archive_url":null,"date":"2017-09-13T09:02:45","subject":"Re: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing\n\tmodes.","submitter":{"id":66284,"url":"http://patchwork.ozlabs.org/api/people/66284/","name":"Kyrill Tkachov","email":"kyrylo.tkachov@foss.arm.com"},"content":"Hi Charles,\n\nOn 12/09/17 09:34, charles.baylis@linaro.org wrote:\n> From: Charles Baylis \n>\n> This patch adds support for modelling the varying costs of\n> different addressing modes. The generic cost table treats\n> all addressing modes as having equal cost.\n>\n> gcc/ChangeLog:\n>\n> Charles Baylis \n>\n> * config/arm/arm-protos.h (enum arm_addr_mode_op): New.\n> (struct addr_mode_cost_table): New.\n> (struct tune_params): Add field addr_mode_costs.\n> * config/arm/arm.c (generic_addr_mode_costs): New.\n> (arm_slowmul_tune): Initialise addr_mode_costs field.\n> (arm_fastmul_tune): Likewise.\n> (arm_strongarm_tune): Likewise.\n> (arm_xscale_tune): Likewise.\n> (arm_9e_tune): Likewise.\n> (arm_marvell_pj4_tune): Likewise.\n> (arm_v6t2_tune): Likewise.\n> (arm_cortex_tune): Likewise.\n> (arm_cortex_a8_tune): Likewise.\n> (arm_cortex_a7_tune): Likewise.\n> (arm_cortex_a15_tune): Likewise.\n> (arm_cortex_a35_tune): Likewise.\n> (arm_cortex_a53_tune): Likewise.\n> (arm_cortex_a57_tune): Likewise.\n> (arm_exynosm1_tune): Likewise.\n> (arm_xgene1_tune): Likewise.\n> (arm_cortex_a5_tune): Likewise.\n> (arm_cortex_a9_tune): Likewise.\n> (arm_cortex_a12_tune): Likewise.\n> (arm_cortex_a73_tune): Likewise.\n> (arm_v7m_tune): Likewise.\n> (arm_cortex_m7_tune): Likewise.\n> (arm_v6m_tune): Likewise.\n> (arm_fa726te_tune): Likewise.\n> (arm_mem_costs): Use table lookup to calculate cost of addressing\n> mode.\n>\n> Change-Id: If71bd7c4f4bb876c5ed82dc28791130efb8bf89e\n> ---\n> gcc/config/arm/arm-protos.h | 20 +++++++++++\n> gcc/config/arm/arm.c | 83 \n> ++++++++++++++++++++++++++++++++++++++++++++-\n> 2 files changed, 102 insertions(+), 1 deletion(-)\n>\n> diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h\n> index 47a85cc..3d6b515 100644\n> --- a/gcc/config/arm/arm-protos.h\n> +++ b/gcc/config/arm/arm-protos.h\n> @@ -261,12 +261,32 @@ struct cpu_vec_costs {\n>\n> struct cpu_cost_table;\n>\n> +/* Addressing mode operations. Used to index tables in struct\n> + addr_mode_cost_table. */\n> +enum arm_addr_mode_op\n> +{\n> + AMO_DEFAULT,\n> + AMO_NO_WB, /* Offset with no writeback. */\n> + AMO_WB, /* Offset with writeback. */\n> + AMO_MAX /* For array size. */\n> +};\n> +\n> +/* Table of additional costs when using addressing modes for each\n> + access type. */\n\nPlease add a comment here saying that the units are in COSTS_N_INSNS\nso that we can reduce the temptation to use these in inappropriate contexts.\n\n> +struct addr_mode_cost_table\n> +{\n> + const int integer[AMO_MAX];\n> + const int fp[AMO_MAX];\n> + const int vector[AMO_MAX];\n> +};\n> +\n> /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this\n> structure is modified. */\n>\n> struct tune_params\n> {\n> const struct cpu_cost_table *insn_extra_cost;\n> + const struct addr_mode_cost_table *addr_mode_costs;\n> bool (*sched_adjust_cost) (rtx_insn *, int, rtx_insn *, int *);\n> int (*branch_cost) (bool, bool);\n> /* Vectorizer costs. */\n> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\n> index b8dbed6..0d31f5f 100644\n> --- a/gcc/config/arm/arm.c\n> +++ b/gcc/config/arm/arm.c\n> @@ -1751,9 +1751,32 @@ const struct cpu_cost_table v7m_extra_costs =\n> }\n> };\n>\n> +const struct addr_mode_cost_table generic_addr_mode_costs =\n> +{\n> + /* int. */\n> + {\n> + 0, /* AMO_DEFAULT. */\n> + 0, /* AMO_NO_WB. */\n> + 0 /* AMO_WB. */\n> + },\n> + /* float. */\n> + {\n> + 0, /* AMO_DEFAULT. */\n> + 0, /* AMO_NO_WB. */\n> + 0 /* AMO_WB. */\n> + },\n> + /* vector. */\n> + {\n> + 0, /* AMO_DEFAULT. */\n> + 0, /* AMO_NO_WB. */\n> + 0 /* AMO_WB. */\n> + }\n> +};\n> +\n> const struct tune_params arm_slowmul_tune =\n> {\n> &generic_extra_costs, /* Insn extra costs. */\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1777,6 +1800,7 @@ const struct tune_params arm_slowmul_tune =\n> const struct tune_params arm_fastmul_tune =\n> {\n> &generic_extra_costs, /* Insn extra costs. */\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1803,6 +1827,7 @@ const struct tune_params arm_fastmul_tune =\n> const struct tune_params arm_strongarm_tune =\n> {\n> &generic_extra_costs, /* Insn extra costs. */\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1826,6 +1851,7 @@ const struct tune_params arm_strongarm_tune =\n> const struct tune_params arm_xscale_tune =\n> {\n> &generic_extra_costs, /* Insn extra costs. */\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> xscale_sched_adjust_cost,\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1849,6 +1875,7 @@ const struct tune_params arm_xscale_tune =\n> const struct tune_params arm_9e_tune =\n> {\n> &generic_extra_costs, /* Insn extra costs. */\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1872,6 +1899,7 @@ const struct tune_params arm_9e_tune =\n> const struct tune_params arm_marvell_pj4_tune =\n> {\n> &generic_extra_costs, /* Insn extra costs. */\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1895,6 +1923,7 @@ const struct tune_params arm_marvell_pj4_tune =\n> const struct tune_params arm_v6t2_tune =\n> {\n> &generic_extra_costs, /* Insn extra costs. */\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1920,6 +1949,7 @@ const struct tune_params arm_v6t2_tune =\n> const struct tune_params arm_cortex_tune =\n> {\n> &generic_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1943,6 +1973,7 @@ const struct tune_params arm_cortex_tune =\n> const struct tune_params arm_cortex_a8_tune =\n> {\n> &cortexa8_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1966,6 +1997,7 @@ const struct tune_params arm_cortex_a8_tune =\n> const struct tune_params arm_cortex_a7_tune =\n> {\n> &cortexa7_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -1989,6 +2021,7 @@ const struct tune_params arm_cortex_a7_tune =\n> const struct tune_params arm_cortex_a15_tune =\n> {\n> &cortexa15_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2012,6 +2045,7 @@ const struct tune_params arm_cortex_a15_tune =\n> const struct tune_params arm_cortex_a35_tune =\n> {\n> &cortexa53_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2035,6 +2069,7 @@ const struct tune_params arm_cortex_a35_tune =\n> const struct tune_params arm_cortex_a53_tune =\n> {\n> &cortexa53_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2058,6 +2093,7 @@ const struct tune_params arm_cortex_a53_tune =\n> const struct tune_params arm_cortex_a57_tune =\n> {\n> &cortexa57_extra_costs,\n> + &generic_addr_mode_costs, /* addressing mode costs */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2081,6 +2117,7 @@ const struct tune_params arm_cortex_a57_tune =\n> const struct tune_params arm_exynosm1_tune =\n> {\n> &exynosm1_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode \n> costs. */\n> NULL, /* Sched adj \n> cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2104,6 +2141,7 @@ const struct tune_params arm_exynosm1_tune =\n> const struct tune_params arm_xgene1_tune =\n> {\n> &xgene1_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2130,6 +2168,7 @@ const struct tune_params arm_xgene1_tune =\n> const struct tune_params arm_cortex_a5_tune =\n> {\n> &cortexa5_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_cortex_a5_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2153,6 +2192,7 @@ const struct tune_params arm_cortex_a5_tune =\n> const struct tune_params arm_cortex_a9_tune =\n> {\n> &cortexa9_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> cortex_a9_sched_adjust_cost,\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2176,6 +2216,7 @@ const struct tune_params arm_cortex_a9_tune =\n> const struct tune_params arm_cortex_a12_tune =\n> {\n> &cortexa12_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost, /* Vectorizer costs. */\n> @@ -2199,6 +2240,7 @@ const struct tune_params arm_cortex_a12_tune =\n> const struct tune_params arm_cortex_a73_tune =\n> {\n> &cortexa57_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode \n> costs. */\n> NULL, /* Sched adj \n> cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost, /* Vectorizer costs. */\n> @@ -2229,6 +2271,7 @@ const struct tune_params arm_cortex_a73_tune =\n> const struct tune_params arm_v7m_tune =\n> {\n> &v7m_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_cortex_m_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2254,6 +2297,7 @@ const struct tune_params arm_v7m_tune =\n> const struct tune_params arm_cortex_m7_tune =\n> {\n> &v7m_extra_costs,\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_cortex_m7_branch_cost,\n> &arm_default_vec_cost,\n> @@ -2280,6 +2324,7 @@ const struct tune_params arm_cortex_m7_tune =\n> const struct tune_params arm_v6m_tune =\n> {\n> &generic_extra_costs, /* Insn extra costs. */\n> + &generic_addr_mode_costs, /* Addressing mode costs. */\n> NULL, /* Sched adj cost. */\n> arm_default_branch_cost,\n> &arm_default_vec_cost, /* Vectorizer costs. */\n> @@ -2303,6 +2348,7 @@ const struct tune_params arm_v6m_tune =\n> const struct tune_params arm_fa726te_tune =\n> {\n> &generic_extra_costs, /* Insn extra costs. */\n> + &generic_addr_mode_costs, /* Addressing mode \n> costs. */\n> fa726te_sched_adjust_cost,\n> arm_default_branch_cost,\n> &arm_default_vec_cost,\n> @@ -9249,7 +9295,42 @@ arm_mem_costs (rtx x, const struct \n> cpu_cost_table *extra_cost,\n> /* Calculate cost of the addressing mode. */\n> if (speed_p)\n> {\n> - /* TODO: Add table-driven costs for addressing modes. (See \n> patch 2) */\n> + arm_addr_mode_op op_type;\n> + switch (GET_CODE (XEXP (x, 0)))\n> + {\n> + default:\n> + case REG:\n> + op_type = AMO_DEFAULT;\n> + break;\n> + case MINUS:\n> + /* MINUS does not appear in RTL, but the architecture \n> supports it,\n> + so handle this case defensively. */\n> + /* fall through */\n> + case PLUS:\n> + op_type = AMO_NO_WB;\n> + break;\n> + case PRE_INC:\n> + case PRE_DEC:\n> + case POST_INC:\n> + case POST_DEC:\n> + case PRE_MODIFY:\n> + case POST_MODIFY:\n> + op_type = AMO_WB;\n> + break;\n> + }\n> +\n> + if (VECTOR_MODE_P (mode))\n> + {\n> + *cost += current_tune->addr_mode_costs->vector[op_type];\n> + }\n> + else if (FLOAT_MODE_P (mode))\n> + {\n> + *cost += current_tune->addr_mode_costs->fp[op_type];\n> + }\n> + else\n> + {\n> + *cost += current_tune->addr_mode_costs->integer[op_type];\n> + }\n\nNo need for brackets for single-statement conditionals.\n\nThis is okay once the prerequisites are committed.\nKyrill\n\n> }\n>\n> /* Calculate cost of memory access. */\n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=temptation","X-HELO":"foss.arm.com","Message-ID":"<59B8F435.7000706@foss.arm.com>","Date":"Wed, 13 Sep 2017 10:02:45 +0100","From":"Kyrill Tkachov ","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:31.0) Gecko/20100101 Thunderbird/31.2.0","MIME-Version":"1.0","To":"\"charles.baylis@linaro.org\" ,\n\tRichard Earnshaw ,\n\tRamana Radhakrishnan ,\n\t\"pinskia@gmail.com\" ","CC":"\"gcc-patches@gcc.gnu.org\" ","Subject":"Re: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing\n\tmodes.","References":"<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>\n\t<1505205277-26276-4-git-send-email-charles.baylis@linaro.org>","In-Reply-To":"<1505205277-26276-4-git-send-email-charles.baylis@linaro.org>","Content-Type":"text/plain; charset=windows-1252; format=flowed","Content-Transfer-Encoding":"7bit"}},{"id":1769257,"web_url":"http://patchwork.ozlabs.org/comment/1769257/","msgid":"","list_archive_url":null,"date":"2017-09-15T15:38:27","subject":"Re: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing\n\tmodes.","submitter":{"id":35578,"url":"http://patchwork.ozlabs.org/api/people/35578/","name":"Charles Baylis","email":"charles.baylis@linaro.org"},"content":"On 13 September 2017 at 10:02, Kyrill Tkachov\n wrote:\n\n>\n> Please add a comment here saying that the units are in COSTS_N_INSNS\n> so that we can reduce the temptation to use these in inappropriate contexts.\n\n>> + if (VECTOR_MODE_P (mode))\n>> + {\n>> + *cost += current_tune->addr_mode_costs->vector[op_type];\n>> + }\n>> + else if (FLOAT_MODE_P (mode))\n>> + {\n>> + *cost += current_tune->addr_mode_costs->fp[op_type];\n>> + }\n>> + else\n>> + {\n>> + *cost += current_tune->addr_mode_costs->integer[op_type];\n>> + }\n>\n>\n> No need for brackets for single-statement conditionals.\n\nDone.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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Fri, 15 Sep 2017 08:38:27 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:cc:content-type; q=dns; s=default; b=onxFulHamO+Pg1h\n\tnj76LggbJS6r/1G8XI2b9uoJ6YPTHDkCTGaGzTxaNwPL1xUSPPm9Q4UElc5xfiAm\n\t5cjqK3eXWF6oGTk2TSfiXHn+YQgeDeSCaWAQWRWpBoWeaCt/agj33OmUj1Fi3EEB\n\tstAm+CGYEjRQffaY+a2AkmZfSsF0=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:cc:content-type; s=default; bh=9SXZ8kCdeoMsj7bB7iaFO\n\ta0/Uck=; b=KtGyt3b0MCT72aToMHhSGhCPNnMF1mF+AVnlW0tIsM8PX6U/hphyi\n\tUPlmhKGs6z2KtXNOD8jDS4R1B5rlqsoJJEEyIY+Ib19dpVAIIkIuCwo7fMutOQuc\n\tBkuUUIGvaJWnfKbtn8pdE7YCEFx43cKiM18NtKc4InKtrLMKLhxAL8=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-1.4 required=5.0 tests=BAYES_00,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM,\n\tSPF_PASS autolearn=no version=3.3.2 spammy=","X-HELO":"mail-io0-f169.google.com","X-Google-DKIM-Signature":"v=1; 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charset=\"UTF-8\"","X-IsSubscribed":"yes"}},{"id":1769259,"web_url":"http://patchwork.ozlabs.org/comment/1769259/","msgid":"","list_archive_url":null,"date":"2017-09-15T15:38:27","subject":"Re: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing\n\tmodes.","submitter":{"id":35578,"url":"http://patchwork.ozlabs.org/api/people/35578/","name":"Charles Baylis","email":"charles.baylis@linaro.org"},"content":"On 13 September 2017 at 10:02, Kyrill Tkachov\n wrote:\n\n>\n> Please add a comment here saying that the units are in COSTS_N_INSNS\n> so that we can reduce the temptation to use these in inappropriate contexts.\n\n>> + if (VECTOR_MODE_P (mode))\n>> + {\n>> + *cost += current_tune->addr_mode_costs->vector[op_type];\n>> + }\n>> + else if (FLOAT_MODE_P (mode))\n>> + {\n>> + *cost += current_tune->addr_mode_costs->fp[op_type];\n>> + }\n>> + else\n>> + {\n>> + *cost += current_tune->addr_mode_costs->integer[op_type];\n>> + }\n>\n>\n> No need for brackets for single-statement conditionals.\n\nDone.\nFrom a35fa59f4dc3be42a52519a90bdd2d47e74db086 Mon Sep 17 00:00:00 2001\nFrom: Charles Baylis \nDate: Thu, 14 Sep 2017 12:47:41 +0100\nSubject: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing modes.\n\nThis patch adds support for modelling the varying costs of\ndifferent addressing modes. The generic cost table treats\nall addressing modes as having equal cost.\n\ngcc/ChangeLog:\n\n Charles Baylis \n\n\t* config/arm/arm-protos.h (enum arm_addr_mode_op): New.\n\t(struct addr_mode_cost_table): New.\n\t(struct tune_params): Add field addr_mode_costs.\n\t* config/arm/arm.c (generic_addr_mode_costs): New.\n\t(arm_slowmul_tune): Initialise addr_mode_costs field.\n\t(arm_fastmul_tune): Likewise.\n\t(arm_strongarm_tune): Likewise.\n\t(arm_xscale_tune): Likewise.\n\t(arm_9e_tune): Likewise.\n\t(arm_marvell_pj4_tune): Likewise.\n\t(arm_v6t2_tune): Likewise.\n\t(arm_cortex_tune): Likewise.\n\t(arm_cortex_a8_tune): Likewise.\n\t(arm_cortex_a7_tune): Likewise.\n\t(arm_cortex_a15_tune): Likewise.\n\t(arm_cortex_a35_tune): Likewise.\n\t(arm_cortex_a53_tune): Likewise.\n\t(arm_cortex_a57_tune): Likewise.\n\t(arm_exynosm1_tune): Likewise.\n\t(arm_xgene1_tune): Likewise.\n\t(arm_cortex_a5_tune): Likewise.\n\t(arm_cortex_a9_tune): Likewise.\n\t(arm_cortex_a12_tune): Likewise.\n\t(arm_cortex_a73_tune): Likewise.\n\t(arm_v7m_tune): Likewise.\n\t(arm_cortex_m7_tune): Likewise.\n\t(arm_v6m_tune): Likewise.\n\t(arm_fa726te_tune): Likewise.\n\t(arm_mem_costs): Use table lookup to calculate cost of addressing\n\tmode.\n\nChange-Id: If71bd7c4f4bb876c5ed82dc28791130efb8bf89e\n---\n gcc/config/arm/arm-protos.h | 20 +++++++++++\n gcc/config/arm/arm.c | 81 +++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 101 insertions(+)\n\ndiff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h\nindex 47a85cc..7769726 100644\n--- a/gcc/config/arm/arm-protos.h\n+++ b/gcc/config/arm/arm-protos.h\n@@ -261,12 +261,32 @@ struct cpu_vec_costs {\n \n struct cpu_cost_table;\n \n+/* Addressing mode operations. Used to index tables in struct\n+ addr_mode_cost_table. */\n+enum arm_addr_mode_op\n+{\n+ AMO_DEFAULT,\n+ AMO_NO_WB,\t/* Offset with no writeback. */\n+ AMO_WB,\t/* Offset with writeback. */\n+ AMO_MAX\t/* For array size. */\n+};\n+\n+/* Table of additional costs in units of COSTS_N_INSNS() when using\n+ addressing modes for each access type. */\n+struct addr_mode_cost_table\n+{\n+ const int integer[AMO_MAX];\n+ const int fp[AMO_MAX];\n+ const int vector[AMO_MAX];\n+};\n+\n /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this\n structure is modified. */\n \n struct tune_params\n {\n const struct cpu_cost_table *insn_extra_cost;\n+ const struct addr_mode_cost_table *addr_mode_costs;\n bool (*sched_adjust_cost) (rtx_insn *, int, rtx_insn *, int *);\n int (*branch_cost) (bool, bool);\n /* Vectorizer costs. */\ndiff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\nindex 64230b8..7773ec3 100644\n--- a/gcc/config/arm/arm.c\n+++ b/gcc/config/arm/arm.c\n@@ -1751,9 +1751,32 @@ const struct cpu_cost_table v7m_extra_costs =\n }\n };\n \n+const struct addr_mode_cost_table generic_addr_mode_costs =\n+{\n+ /* int. */\n+ {\n+ COSTS_N_INSNS (0),\t/* AMO_DEFAULT. */\n+ COSTS_N_INSNS (0),\t/* AMO_NO_WB. */\n+ COSTS_N_INSNS (0)\t/* AMO_WB. */\n+ },\n+ /* float. */\n+ {\n+ COSTS_N_INSNS (0),\t/* AMO_DEFAULT. */\n+ COSTS_N_INSNS (0),\t/* AMO_NO_WB. */\n+ COSTS_N_INSNS (0)\t/* AMO_WB. */\n+ },\n+ /* vector. */\n+ {\n+ COSTS_N_INSNS (0),\t/* AMO_DEFAULT. */\n+ COSTS_N_INSNS (0),\t/* AMO_NO_WB. */\n+ COSTS_N_INSNS (0)\t/* AMO_WB. */\n+ }\n+};\n+\n const struct tune_params arm_slowmul_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1777,6 +1800,7 @@ const struct tune_params arm_slowmul_tune =\n const struct tune_params arm_fastmul_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1803,6 +1827,7 @@ const struct tune_params arm_fastmul_tune =\n const struct tune_params arm_strongarm_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1826,6 +1851,7 @@ const struct tune_params arm_strongarm_tune =\n const struct tune_params arm_xscale_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n xscale_sched_adjust_cost,\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1849,6 +1875,7 @@ const struct tune_params arm_xscale_tune =\n const struct tune_params arm_9e_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1872,6 +1899,7 @@ const struct tune_params arm_9e_tune =\n const struct tune_params arm_marvell_pj4_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1895,6 +1923,7 @@ const struct tune_params arm_marvell_pj4_tune =\n const struct tune_params arm_v6t2_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1920,6 +1949,7 @@ const struct tune_params arm_v6t2_tune =\n const struct tune_params arm_cortex_tune =\n {\n &generic_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1943,6 +1973,7 @@ const struct tune_params arm_cortex_tune =\n const struct tune_params arm_cortex_a8_tune =\n {\n &cortexa8_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1966,6 +1997,7 @@ const struct tune_params arm_cortex_a8_tune =\n const struct tune_params arm_cortex_a7_tune =\n {\n &cortexa7_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -1989,6 +2021,7 @@ const struct tune_params arm_cortex_a7_tune =\n const struct tune_params arm_cortex_a15_tune =\n {\n &cortexa15_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2012,6 +2045,7 @@ const struct tune_params arm_cortex_a15_tune =\n const struct tune_params arm_cortex_a35_tune =\n {\n &cortexa53_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2035,6 +2069,7 @@ const struct tune_params arm_cortex_a35_tune =\n const struct tune_params arm_cortex_a53_tune =\n {\n &cortexa53_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2058,6 +2093,7 @@ const struct tune_params arm_cortex_a53_tune =\n const struct tune_params arm_cortex_a57_tune =\n {\n &cortexa57_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* addressing mode costs */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2081,6 +2117,7 @@ const struct tune_params arm_cortex_a57_tune =\n const struct tune_params arm_exynosm1_tune =\n {\n &exynosm1_extra_costs,\n+ &generic_addr_mode_costs,\t\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2104,6 +2141,7 @@ const struct tune_params arm_exynosm1_tune =\n const struct tune_params arm_xgene1_tune =\n {\n &xgene1_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2130,6 +2168,7 @@ const struct tune_params arm_xgene1_tune =\n const struct tune_params arm_cortex_a5_tune =\n {\n &cortexa5_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_cortex_a5_branch_cost,\n &arm_default_vec_cost,\n@@ -2153,6 +2192,7 @@ const struct tune_params arm_cortex_a5_tune =\n const struct tune_params arm_cortex_a9_tune =\n {\n &cortexa9_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n cortex_a9_sched_adjust_cost,\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -2176,6 +2216,7 @@ const struct tune_params arm_cortex_a9_tune =\n const struct tune_params arm_cortex_a12_tune =\n {\n &cortexa12_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost, /* Vectorizer costs. */\n@@ -2199,6 +2240,7 @@ const struct tune_params arm_cortex_a12_tune =\n const struct tune_params arm_cortex_a73_tune =\n {\n &cortexa57_extra_costs,\n+ &generic_addr_mode_costs,\t\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost,\t\t\t/* Vectorizer costs. */\n@@ -2229,6 +2271,7 @@ const struct tune_params arm_cortex_a73_tune =\n const struct tune_params arm_v7m_tune =\n {\n &v7m_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_cortex_m_branch_cost,\n &arm_default_vec_cost,\n@@ -2254,6 +2297,7 @@ const struct tune_params arm_v7m_tune =\n const struct tune_params arm_cortex_m7_tune =\n {\n &v7m_extra_costs,\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_cortex_m7_branch_cost,\n &arm_default_vec_cost,\n@@ -2280,6 +2324,7 @@ const struct tune_params arm_cortex_m7_tune =\n const struct tune_params arm_v6m_tune =\n {\n &generic_extra_costs,\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t/* Addressing mode costs. */\n NULL,\t\t\t\t\t/* Sched adj cost. */\n arm_default_branch_cost,\n &arm_default_vec_cost, /* Vectorizer costs. */\n@@ -2303,6 +2348,7 @@ const struct tune_params arm_v6m_tune =\n const struct tune_params arm_fa726te_tune =\n {\n &generic_extra_costs,\t\t\t\t/* Insn extra costs. */\n+ &generic_addr_mode_costs,\t\t\t/* Addressing mode costs. */\n fa726te_sched_adjust_cost,\n arm_default_branch_cost,\n &arm_default_vec_cost,\n@@ -9247,6 +9293,41 @@ arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost,\n below. See arm.md:calculate_pic_address. */\n *cost += COSTS_N_INSNS (1);\n \n+ /* Calculate cost of the addressing mode. */\n+ if (speed_p)\n+ {\n+ arm_addr_mode_op op_type;\n+ switch (GET_CODE (XEXP (x, 0)))\n+\t{\n+\tdefault:\n+\tcase REG:\n+\t op_type = AMO_DEFAULT;\n+\t break;\n+\tcase MINUS:\n+\t /* MINUS does not appear in RTL, but the architecture supports it,\n+\t so handle this case defensively. */\n+\t /* fall through */\n+\tcase PLUS:\n+\t op_type = AMO_NO_WB;\n+\t break;\n+\tcase PRE_INC:\n+\tcase PRE_DEC:\n+\tcase POST_INC:\n+\tcase POST_DEC:\n+\tcase PRE_MODIFY:\n+\tcase POST_MODIFY:\n+\t op_type = AMO_WB;\n+\t break;\n+\t}\n+\n+ if (VECTOR_MODE_P (mode))\n+\t *cost += current_tune->addr_mode_costs->vector[op_type];\n+ else if (FLOAT_MODE_P (mode))\n+\t *cost += current_tune->addr_mode_costs->fp[op_type];\n+ else\n+\t *cost += current_tune->addr_mode_costs->integer[op_type];\n+ }\n+\n /* Calculate cost of memory access. */\n if (speed_p)\n {","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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boundary=\"94eb2c05b10e3003e405593c2f9d\"","X-IsSubscribed":"yes"}},{"id":1769304,"web_url":"http://patchwork.ozlabs.org/comment/1769304/","msgid":"<59BC0689.60602@foss.arm.com>","list_archive_url":null,"date":"2017-09-15T16:57:45","subject":"Re: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing\n\tmodes.","submitter":{"id":66284,"url":"http://patchwork.ozlabs.org/api/people/66284/","name":"Kyrill Tkachov","email":"kyrylo.tkachov@foss.arm.com"},"content":"On 15/09/17 16:38, Charles Baylis wrote:\n> On 13 September 2017 at 10:02, Kyrill Tkachov\n> wrote:\n>\n>> Please add a comment here saying that the units are in COSTS_N_INSNS\n>> so that we can reduce the temptation to use these in inappropriate contexts.\n>>> + if (VECTOR_MODE_P (mode))\n>>> + {\n>>> + *cost += current_tune->addr_mode_costs->vector[op_type];\n>>> + }\n>>> + else if (FLOAT_MODE_P (mode))\n>>> + {\n>>> + *cost += current_tune->addr_mode_costs->fp[op_type];\n>>> + }\n>>> + else\n>>> + {\n>>> + *cost += current_tune->addr_mode_costs->integer[op_type];\n>>> + }\n>>\n>> No need for brackets for single-statement conditionals.\n> Done.\n\nThanks, this is ok once the prerequisites are sorted.\n\nKyrill","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-0.9 required=5.0 tests=BAYES_00,\n\tKAM_LAZY_DOMAIN_SECURITY,\n\tRP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=","X-HELO":"foss.arm.com","Message-ID":"<59BC0689.60602@foss.arm.com>","Date":"Fri, 15 Sep 2017 17:57:45 +0100","From":"Kyrill Tkachov ","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:31.0) Gecko/20100101 Thunderbird/31.2.0","MIME-Version":"1.0","To":"Charles Baylis ","CC":"Richard Earnshaw ,\n\tRamana Radhakrishnan ,\n\t\"pinskia@gmail.com\" ,\n\t\"gcc-patches@gcc.gnu.org\" ","Subject":"Re: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing\n\tmodes.","References":"<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>\n\t<1505205277-26276-4-git-send-email-charles.baylis@linaro.org>\n\t<59B8F435.7000706@foss.arm.com>\n\t","In-Reply-To":"","Content-Type":"text/plain; charset=windows-1252; format=flowed","Content-Transfer-Encoding":"7bit"}},{"id":1809453,"web_url":"http://patchwork.ozlabs.org/comment/1809453/","msgid":"","list_archive_url":null,"date":"2017-11-23T18:53:38","subject":"Re: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing\n\tmodes.","submitter":{"id":35578,"url":"http://patchwork.ozlabs.org/api/people/35578/","name":"Charles Baylis","email":"charles.baylis@linaro.org"},"content":"On 15 September 2017 at 17:57, Kyrill Tkachov\n wrote:\n>\n> Thanks, this is ok once the prerequisites are sorted.\n\nPatch 1 was abandoned, and a later version of patch 2 has been\ncommitted, so this was applied to trunk as r255112.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-467809-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; 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