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GET /api/patches/806602/?format=api
{ "id": 806602, "url": "http://patchwork.ozlabs.org/api/patches/806602/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828142307.30061-2-l.stach@pengutronix.de/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170828142307.30061-2-l.stach@pengutronix.de>", "list_archive_url": null, "date": "2017-08-28T14:23:05", "name": "[1/3] PCI: designware: only register MSI controller when MSI irq line is valid", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "6002b2a41f977220615bdaf7cf71902b90f32bf7", "submitter": { "id": 23583, "url": "http://patchwork.ozlabs.org/api/people/23583/?format=api", "name": "Lucas Stach", "email": "l.stach@pengutronix.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828142307.30061-2-l.stach@pengutronix.de/mbox/", "series": [ { "id": 182, "url": "http://patchwork.ozlabs.org/api/series/182/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=182", "date": "2017-08-28T14:23:05", "name": "DWC host without MSI controller", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/182/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806602/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806602/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgvBZ3xjyz9sMN\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 00:23:18 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751470AbdH1OXP (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 10:23:15 -0400", "from metis.ext.4.pengutronix.de ([92.198.50.35]:36777 \"EHLO\n\tmetis.ext.4.pengutronix.de\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1751302AbdH1OXM (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Mon, 28 Aug 2017 10:23:12 -0400", "from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]\n\thelo=dude.pengutronix.de.)\n\tby metis.ext.pengutronix.de with esmtp (Exim 4.84_2)\n\t(envelope-from <l.stach@pengutronix.de>)\n\tid 1dmKwX-0005gz-9c; Mon, 28 Aug 2017 16:23:09 +0200" ], "From": "Lucas Stach <l.stach@pengutronix.de>", "To": "Bjorn Helgaas <bhelgaas@google.com>, Tim Harvey <tharvey@gateworks.com>,\n\tJingoo Han <jingoohan1@gmail.com>, Joao Pinto <Joao.Pinto@synopsys.com>,\n\tShawn Guo <shawnguo@kernel.org>", "Cc": "linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tpatchwork-lst@pengutronix.de, kernel@pengutronix.de", "Subject": "[PATCH 1/3] PCI: designware: only register MSI controller when MSI\n\tirq line is valid", "Date": "Mon, 28 Aug 2017 16:23:05 +0200", "Message-Id": "<20170828142307.30061-2-l.stach@pengutronix.de>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170828142307.30061-1-l.stach@pengutronix.de>", "References": "<20170828142307.30061-1-l.stach@pengutronix.de>", "X-SA-Exim-Connect-IP": "2001:67c:670:100:1d::7", "X-SA-Exim-Mail-From": "l.stach@pengutronix.de", "X-SA-Exim-Scanned": "No (on metis.ext.pengutronix.de);\n\tSAEximRunCond expanded to false", "X-PTX-Original-Recipient": "linux-pci@vger.kernel.org", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "The MSI part of the controller isn't essential, so the host controller can\nbe registered without the MSI controller being present. This allows the\nhost to work in PCIe legancy interrupt only mode, if the IRQ line for the\nMSI controller is missing.\n\nSigned-off-by: Lucas Stach <l.stach@pengutronix.de>\n---\n drivers/pci/dwc/pcie-designware-host.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c\nindex d29c020da082..8494089f088d 100644\n--- a/drivers/pci/dwc/pcie-designware-host.c\n+++ b/drivers/pci/dwc/pcie-designware-host.c\n@@ -381,7 +381,7 @@ int dw_pcie_host_init(struct pcie_port *pp)\n \tif (ret)\n \t\tpci->num_viewport = 2;\n \n-\tif (IS_ENABLED(CONFIG_PCI_MSI)) {\n+\tif (IS_ENABLED(CONFIG_PCI_MSI) && pp->msi_irq > 0) {\n \t\tif (!pp->ops->msi_host_init) {\n \t\t\tpp->irq_domain = irq_domain_add_linear(dev->of_node,\n \t\t\t\t\t\tMAX_MSI_IRQS, &msi_domain_ops,\n@@ -412,7 +412,7 @@ int dw_pcie_host_init(struct pcie_port *pp)\n \tbridge->ops = &dw_pcie_ops;\n \tbridge->map_irq = of_irq_parse_and_map_pci;\n \tbridge->swizzle_irq = pci_common_swizzle;\n-\tif (IS_ENABLED(CONFIG_PCI_MSI)) {\n+\tif (IS_ENABLED(CONFIG_PCI_MSI) && pp->msi_irq > 0) {\n \t\tbridge->msi = &dw_pcie_msi_chip;\n \t\tdw_pcie_msi_chip.dev = dev;\n \t}\n", "prefixes": [ "1/3" ] }