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GET /api/1.2/series/500355/?format=api
{ "id": 500355, "url": "http://patchwork.ozlabs.org/api/1.2/series/500355/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500355", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "name": "Add RISC-V big-endian target support", "date": "2026-04-17T14:49:12", "submitter": { "id": 90738, "url": "http://patchwork.ozlabs.org/api/1.2/people/90738/?format=api", "name": "Djordje Todorovic", "email": "Djordje.Todorovic@htecgroup.com" }, "version": 8, "total": 7, "received_total": 7, "received_all": true, "mbox": "http://patchwork.ozlabs.org/series/500355/mbox/", "cover_letter": { "id": 2224534, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2224534/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260417144905.178056-1-djordje.todorovic@htecgroup.com/", "msgid": "<20260417144905.178056-1-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T14:49:12", "name": "[v8,0/7] Add RISC-V big-endian target support", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260417144905.178056-1-djordje.todorovic@htecgroup.com/mbox/" }, "patches": [ { "id": 2224532, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224532/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-2-djordje.todorovic@htecgroup.com/", "msgid": "<20260417144905.178056-2-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T14:49:12", "name": "[v8,1/7] target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-2-djordje.todorovic@htecgroup.com/mbox/" }, { "id": 2224539, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224539/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-6-djordje.todorovic@htecgroup.com/", "msgid": "<20260417144905.178056-6-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T14:49:13", "name": "[v8,5/7] target/riscv: Fix page table walk endianness for big-endian harts", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-6-djordje.todorovic@htecgroup.com/mbox/" }, { "id": 2224541, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224541/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-3-djordje.todorovic@htecgroup.com/", "msgid": "<20260417144905.178056-3-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T14:49:13", "name": "[v8,2/7] target/riscv: Add big-endian CPU configuration field and reset logic", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-3-djordje.todorovic@htecgroup.com/mbox/" }, { "id": 2224533, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224533/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-5-djordje.todorovic@htecgroup.com/", "msgid": "<20260417144905.178056-5-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T14:49:13", "name": "[v8,4/7] hw/riscv: Make boot code endianness-aware at runtime", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-5-djordje.todorovic@htecgroup.com/mbox/" }, { "id": 2224540, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224540/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-4-djordje.todorovic@htecgroup.com/", "msgid": "<20260417144905.178056-4-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T14:49:13", "name": "[v8,3/7] target/riscv: Implement runtime data endianness via MSTATUS bits", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-4-djordje.todorovic@htecgroup.com/mbox/" }, { "id": 2224544, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224544/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-8-djordje.todorovic@htecgroup.com/", "msgid": "<20260417144905.178056-8-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T14:49:14", "name": "[v8,7/7] target/riscv: Add endianness test for RISC-V BE", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-8-djordje.todorovic@htecgroup.com/mbox/" }, { "id": 2224538, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224538/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-7-djordje.todorovic@htecgroup.com/", "msgid": "<20260417144905.178056-7-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T14:49:14", "name": "[v8,6/7] target/riscv: Expose big-endian CPU property and add documentation", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-7-djordje.todorovic@htecgroup.com/mbox/" } ] }