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GET /api/1.2/patches/2224541/?format=api
{ "id": 2224541, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224541/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-3-djordje.todorovic@htecgroup.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417144905.178056-3-djordje.todorovic@htecgroup.com>", "list_archive_url": null, "date": "2026-04-17T14:49:13", "name": "[v8,2/7] target/riscv: Add big-endian CPU configuration field and reset logic", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9d8b3cf8a2b7da994f707407891a375212896680", "submitter": { "id": 90738, "url": "http://patchwork.ozlabs.org/api/1.2/people/90738/?format=api", "name": "Djordje Todorovic", "email": "Djordje.Todorovic@htecgroup.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417144905.178056-3-djordje.todorovic@htecgroup.com/mbox/", "series": [ { "id": 500355, "url": "http://patchwork.ozlabs.org/api/1.2/series/500355/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500355", "date": "2026-04-17T14:49:12", "name": "Add RISC-V big-endian target support", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/500355/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224541/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224541/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=IaDsdenh;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "htecgroup.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "PA2PR09MB7634.eurprd09.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5e64bc24-db2c-4eab-073c-08de9c907e09", "X-MS-Exchange-CrossTenant-originalarrivaltime": "17 Apr 2026 14:49:13.2220 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "9f85665b-7efd-4776-9dfe-b6bfda2565ee", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n aMDusQyeC2T1TyNIepe4zZsx8IWr6z0DIzGvxYZ9cax9sSCTsMkjkErtKJP1FpSgD5jHA/CVWekTcLFmYk5wPPsF3LzRKHpJRxDlYPEWrqI=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VI0PR09MB8150", "Received-SPF": "pass client-ip=2a01:111:f403:c20a::7;\n envelope-from=Djordje.Todorovic@htecgroup.com;\n helo=PA4PR04CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add a big_endian field to RISCVCPUConfig and wire it into the CPU\nreset path. When cfg.big_endian is set, riscv_cpu_reset_hold()\nwrites 1 into the MSTATUS MBE/SBE/UBE fields using set_field();\notherwise it writes 0. This makes the reset value deterministic on\nboth cold and warm reset.\n\nThe MBE/SBE/UBE bits are not included in the writable mask of any\nmstatus/mstatush/sstatus CSR write path (unchanged by this series),\nso the value chosen at reset effectively hardwires them per section\n3.1.6.5 of the RISC-V Privileged Specification.\n\nThe user-facing property and documentation are added in a later\npatch, once the full endianness support is in place.\n\nAlso update the disassembler comment to clarify that BFD_ENDIAN_LITTLE\nis correct because RISC-V instructions are always little-endian per\nthe ISA specification.\n\nSigned-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>\n---\n target/riscv/cpu.c | 10 +++++-----\n target/riscv/cpu_cfg_fields.h.inc | 1 +\n 2 files changed, 6 insertions(+), 5 deletions(-)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex e56470a374..a32e4fd6d6 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -716,6 +716,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)\n env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1);\n }\n }\n+ env->mstatus = set_field(env->mstatus, MSTATUS_MBE, cpu->cfg.big_endian);\n+ env->mstatus = set_field(env->mstatus, MSTATUS_SBE, cpu->cfg.big_endian);\n+ env->mstatus = set_field(env->mstatus, MSTATUS_UBE, cpu->cfg.big_endian);\n env->mcause = 0;\n env->miclaim = MIP_SGEIP;\n env->pc = env->resetvec;\n@@ -803,11 +806,8 @@ static void riscv_cpu_disas_set_info(const CPUState *s, disassemble_info *info)\n info->target_info = &cpu->cfg;\n \n /*\n- * A couple of bits in MSTATUS set the endianness:\n- * - MSTATUS_UBE (User-mode),\n- * - MSTATUS_SBE (Supervisor-mode),\n- * - MSTATUS_MBE (Machine-mode)\n- * but we don't implement that yet.\n+ * RISC-V instructions are always little-endian, regardless of the\n+ * data endianness configured via MSTATUS UBE/SBE/MBE bits.\n */\n info->endian = BFD_ENDIAN_LITTLE;\n \ndiff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\nindex 70ec650abf..51436daabf 100644\n--- a/target/riscv/cpu_cfg_fields.h.inc\n+++ b/target/riscv/cpu_cfg_fields.h.inc\n@@ -154,6 +154,7 @@ BOOL_FIELD(ext_xmipscbop)\n BOOL_FIELD(ext_xmipscmov)\n BOOL_FIELD(ext_xmipslsp)\n \n+BOOL_FIELD(big_endian)\n BOOL_FIELD(mmu)\n BOOL_FIELD(pmp)\n BOOL_FIELD(debug)\n", "prefixes": [ "v8", "2/7" ] }