diff mbox series

[v2,11/11] net: dwc_eth_qos: Add support for st, ext-phyclk property

Message ID 20240326120745.27581-12-marex@denx.de
State Accepted
Commit 1ef28c58d2dbd8c7d65e28ef500bfd359c66c07f
Delegated to: Patrice Chotard
Headers show
Series net: dwc_eth_qos: Clean up STM32 glue code and add STM32MP13xx support | expand

Commit Message

Marek Vasut March 26, 2024, 12:07 p.m. UTC 
The "st,ext-phyclk" property is a unification of "st,eth-clk-sel"
and "st,eth-ref-clk-sel" properties. All three properties define
ETH CK clock direction, however:
- "st,eth-clk-sel" selects clock direction for GMII/RGMII mode
- "st,eth-ref-clk-sel" selects clock direction for RMII mode
- "st,ext-phyclk" selects clock direction for all RMII/GMII/RGMII modes
The "st,ext-phyclk" is the preferrable property to use.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Christophe Roullier <christophe.roullier@st.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: u-boot@dh-electronics.com
Cc: uboot-stm32@st-md-mailman.stormreply.com
---
V2: New patch
---
 drivers/net/dwc_eth_qos_stm32.c | 30 +++++++++++++++++++++++++++---
 1 file changed, 27 insertions(+), 3 deletions(-)

Comments

Christophe Roullier April 8, 2024, 3:52 p.m. UTC | #1 
> -----Original Message-----
> From: Marek Vasut<marex@denx.de>
> Sent: Tuesday, March 26, 2024 1:08 PM
> To:u-boot@lists.denx.de
> Cc: Marek Vasut<marex@denx.de>; Christophe ROULLIER<christophe.roullier@st.com>; Joe Hershberger<joe.hershberger@ni.com>; Patrice CHOTARD - foss<patrice.chotard@foss.st.com>; Patrick DELAUNAY - foss<patrick.delaunay@foss.st.com>; Ramon Fried<rfried.dev@gmail.com>;u-boot@dh-electronics.com;uboot-stm32@st-md-mailman.stormreply.com
> Subject: [PATCH v2 11/11] net: dwc_eth_qos: Add support for st,ext-phyclk property
>
> The "st,ext-phyclk" property is a unification of "st,eth-clk-sel"
> and "st,eth-ref-clk-sel" properties. All three properties define ETH CK clock direction, however:
> - "st,eth-clk-sel" selects clock direction for GMII/RGMII mode
> - "st,eth-ref-clk-sel" selects clock direction for RMII mode
> - "st,ext-phyclk" selects clock direction for all RMII/GMII/RGMII modes The "st,ext-phyclk" is the preferrable property to use.
>
> Signed-off-by: Marek Vasut<marex@denx.de>
> ---
> Cc: Christophe Roullier<christophe.roullier@st.com>
> Cc: Joe Hershberger<joe.hershberger@ni.com>
> Cc: Patrice Chotard<patrice.chotard@foss.st.com>
> Cc: Patrick Delaunay<patrick.delaunay@foss.st.com>
> Cc: Ramon Fried<rfried.dev@gmail.com>
> Cc:u-boot@dh-electronics.com
> Cc:uboot-stm32@st-md-mailman.stormreply.com
> ---
> V2: New patch
> ---
>   drivers/net/dwc_eth_qos_stm32.c | 30 +++++++++++++++++++++++++++---
>   1 file changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index 435473f99a6..9ee82b54c62 100644
> --- a/drivers/net/dwc_eth_qos_stm32.c
> +++ b/drivers/net/dwc_eth_qos_stm32.c
> @@ -140,6 +140,8 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>          const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac");
>          /* Gigabit Ethernet 125MHz clock selection. */
>          const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
> +       /* Ethernet clock source is RCC. */
> +       const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk");
>          struct regmap *regmap;
>          u32 regmap_mask;
>          u32 value;
> @@ -156,6 +158,12 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>                  dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>                                     SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
> +               /*
> +                * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
> +                * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
> +                * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
> +                * supports only MII, ETH_SELMII is not present.
> +                */
>                  if (!is_mp13)   /* Select MII mode on STM32MP15xx */
>                          value |= SYSCFG_PMCSETR_ETH_SELMII;
>                  break;
> @@ -163,14 +171,25 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>                  dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>                                     SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
> -               if (eth_clk_sel)
> +               /*
> +                * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
> +                * otherwise use external clock from IO pin (requires matching
> +                * GPIO block AF setting of that pin).
> +                */
> +               if (eth_clk_sel || ext_phyclk)
>                          value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
>                  break;
>          case PHY_INTERFACE_MODE_RMII:
>                  dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n");
>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>                                     SYSCFG_PMCSETR_ETH_SEL_RMII);
> -               if (eth_ref_clk_sel)
> +               /*
> +                * If eth_ref_clk_sel is set, use internal clock from RCC,
> +                * otherwise use external clock from ETHn_RX_CLK/ETHn_REF_CLK
> +                * IO pin (requires matching GPIO block AF setting of that
> +                * pin).
> +                */
> +               if (eth_ref_clk_sel || ext_phyclk)
>                          value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
>                  break;
>          case PHY_INTERFACE_MODE_RGMII:
> @@ -180,7 +199,12 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>                  dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n");
>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>                                     SYSCFG_PMCSETR_ETH_SEL_RGMII);
> -               if (eth_clk_sel)
> +               /*
> +                * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
> +                * otherwise use external clock from ETHx_CLK125 pin (requires
> +                * matching GPIO block AF setting of that pin).
> +                */
> +               if (eth_clk_sel || ext_phyclk)
>                          value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
>                  break;
>          default:
> --
> 2.43.0
>
Reviewed-by: Christophe ROULLIER <christophe.roullier@foss.st.com>
Patrice CHOTARD April 19, 2024, 12:11 p.m. UTC | #2 
On 4/8/24 17:52, Christophe ROULLIER wrote:
>> -----Original Message-----
>> From: Marek Vasut<marex@denx.de>
>> Sent: Tuesday, March 26, 2024 1:08 PM
>> To:u-boot@lists.denx.de
>> Cc: Marek Vasut<marex@denx.de>; Christophe ROULLIER<christophe.roullier@st.com>; Joe Hershberger<joe.hershberger@ni.com>; Patrice CHOTARD - foss<patrice.chotard@foss.st.com>; Patrick DELAUNAY - foss<patrick.delaunay@foss.st.com>; Ramon Fried<rfried.dev@gmail.com>;u-boot@dh-electronics.com;uboot-stm32@st-md-mailman.stormreply.com
>> Subject: [PATCH v2 11/11] net: dwc_eth_qos: Add support for st,ext-phyclk property
>>
>> The "st,ext-phyclk" property is a unification of "st,eth-clk-sel"
>> and "st,eth-ref-clk-sel" properties. All three properties define ETH CK clock direction, however:
>> - "st,eth-clk-sel" selects clock direction for GMII/RGMII mode
>> - "st,eth-ref-clk-sel" selects clock direction for RMII mode
>> - "st,ext-phyclk" selects clock direction for all RMII/GMII/RGMII modes The "st,ext-phyclk" is the preferrable property to use.
>>
>> Signed-off-by: Marek Vasut<marex@denx.de>
>> ---
>> Cc: Christophe Roullier<christophe.roullier@st.com>
>> Cc: Joe Hershberger<joe.hershberger@ni.com>
>> Cc: Patrice Chotard<patrice.chotard@foss.st.com>
>> Cc: Patrick Delaunay<patrick.delaunay@foss.st.com>
>> Cc: Ramon Fried<rfried.dev@gmail.com>
>> Cc:u-boot@dh-electronics.com
>> Cc:uboot-stm32@st-md-mailman.stormreply.com
>> ---
>> V2: New patch
>> ---
>>   drivers/net/dwc_eth_qos_stm32.c | 30 +++++++++++++++++++++++++++---
>>   1 file changed, 27 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index 435473f99a6..9ee82b54c62 100644
>> --- a/drivers/net/dwc_eth_qos_stm32.c
>> +++ b/drivers/net/dwc_eth_qos_stm32.c
>> @@ -140,6 +140,8 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>>          const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac");
>>          /* Gigabit Ethernet 125MHz clock selection. */
>>          const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
>> +       /* Ethernet clock source is RCC. */
>> +       const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk");
>>          struct regmap *regmap;
>>          u32 regmap_mask;
>>          u32 value;
>> @@ -156,6 +158,12 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>>                  dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
>>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>>                                     SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
>> +               /*
>> +                * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
>> +                * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
>> +                * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
>> +                * supports only MII, ETH_SELMII is not present.
>> +                */
>>                  if (!is_mp13)   /* Select MII mode on STM32MP15xx */
>>                          value |= SYSCFG_PMCSETR_ETH_SELMII;
>>                  break;
>> @@ -163,14 +171,25 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>>                  dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
>>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>>                                     SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
>> -               if (eth_clk_sel)
>> +               /*
>> +                * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
>> +                * otherwise use external clock from IO pin (requires matching
>> +                * GPIO block AF setting of that pin).
>> +                */
>> +               if (eth_clk_sel || ext_phyclk)
>>                          value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
>>                  break;
>>          case PHY_INTERFACE_MODE_RMII:
>>                  dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n");
>>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>>                                     SYSCFG_PMCSETR_ETH_SEL_RMII);
>> -               if (eth_ref_clk_sel)
>> +               /*
>> +                * If eth_ref_clk_sel is set, use internal clock from RCC,
>> +                * otherwise use external clock from ETHn_RX_CLK/ETHn_REF_CLK
>> +                * IO pin (requires matching GPIO block AF setting of that
>> +                * pin).
>> +                */
>> +               if (eth_ref_clk_sel || ext_phyclk)
>>                          value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
>>                  break;
>>          case PHY_INTERFACE_MODE_RGMII:
>> @@ -180,7 +199,12 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>>                  dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n");
>>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>>                                     SYSCFG_PMCSETR_ETH_SEL_RGMII);
>> -               if (eth_clk_sel)
>> +               /*
>> +                * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
>> +                * otherwise use external clock from ETHx_CLK125 pin (requires
>> +                * matching GPIO block AF setting of that pin).
>> +                */
>> +               if (eth_clk_sel || ext_phyclk)
>>                          value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
>>                  break;
>>          default:
>> -- 
>> 2.43.0
>>
> Reviewed-by: Christophe ROULLIER <christophe.roullier@foss.st.com>

Applied on u-boot-stm32/master
diff mbox series

Patch

diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
index 435473f99a6..9ee82b54c62 100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -140,6 +140,8 @@  static int eqos_probe_syscfg_stm32(struct udevice *dev,
 	const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac");
 	/* Gigabit Ethernet 125MHz clock selection. */
 	const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
+	/* Ethernet clock source is RCC. */
+	const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk");
 	struct regmap *regmap;
 	u32 regmap_mask;
 	u32 value;
@@ -156,6 +158,12 @@  static int eqos_probe_syscfg_stm32(struct udevice *dev,
 		dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
 		value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 				   SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
+		/*
+		 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
+		 * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
+		 * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
+		 * supports only MII, ETH_SELMII is not present.
+		 */
 		if (!is_mp13)	/* Select MII mode on STM32MP15xx */
 			value |= SYSCFG_PMCSETR_ETH_SELMII;
 		break;
@@ -163,14 +171,25 @@  static int eqos_probe_syscfg_stm32(struct udevice *dev,
 		dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
 		value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 				   SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
-		if (eth_clk_sel)
+		/*
+		 * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
+		 * otherwise use external clock from IO pin (requires matching
+		 * GPIO block AF setting of that pin).
+		 */
+		if (eth_clk_sel || ext_phyclk)
 			value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
 		break;
 	case PHY_INTERFACE_MODE_RMII:
 		dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n");
 		value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 				   SYSCFG_PMCSETR_ETH_SEL_RMII);
-		if (eth_ref_clk_sel)
+		/*
+		 * If eth_ref_clk_sel is set, use internal clock from RCC,
+		 * otherwise use external clock from ETHn_RX_CLK/ETHn_REF_CLK
+		 * IO pin (requires matching GPIO block AF setting of that
+		 * pin).
+		 */
+		if (eth_ref_clk_sel || ext_phyclk)
 			value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
 		break;
 	case PHY_INTERFACE_MODE_RGMII:
@@ -180,7 +199,12 @@  static int eqos_probe_syscfg_stm32(struct udevice *dev,
 		dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n");
 		value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 				   SYSCFG_PMCSETR_ETH_SEL_RGMII);
-		if (eth_clk_sel)
+		/*
+		 * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC,
+		 * otherwise use external clock from ETHx_CLK125 pin (requires
+		 * matching GPIO block AF setting of that pin).
+		 */
+		if (eth_clk_sel || ext_phyclk)
 			value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
 		break;
 	default: