diff mbox series

[v2,09/11] net: dwc_eth_qos: Add DT parsing for STM32MP13xx platform

Message ID 20240326120745.27581-10-marex@denx.de
State Accepted
Commit a440d19c6c91938190b329be65e0986e01007304
Delegated to: Patrice Chotard
Headers show
Series net: dwc_eth_qos: Clean up STM32 glue code and add STM32MP13xx support | expand

Commit Message

Marek Vasut March 26, 2024, 12:07 p.m. UTC 
From: Christophe Roullier <christophe.roullier@st.com>

Manage 2 ethernet instances, select which instance to configure with mask
If mask is not present in DT, it is stm32mp15 platform.

Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Rework the code
---
Cc: Christophe Roullier <christophe.roullier@st.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: u-boot@dh-electronics.com
Cc: uboot-stm32@st-md-mailman.stormreply.com
---
V2: - Drop unrelated clock frequency validation
    - Move "st,ext-phyclk" property support into separate patch
    - This leaves only the regmap parts here
---
 drivers/net/dwc_eth_qos_stm32.c | 41 ++++++++++++++++++++++-----------
 1 file changed, 28 insertions(+), 13 deletions(-)

Comments

Christophe Roullier April 8, 2024, 3:50 p.m. UTC | #1 
> -----Original Message-----
> From: Marek Vasut<marex@denx.de>
> Sent: Tuesday, March 26, 2024 1:08 PM
> To:u-boot@lists.denx.de
> Cc: Christophe ROULLIER<christophe.roullier@st.com>; Marek Vasut<marex@denx.de>; Joe Hershberger<joe.hershberger@ni.com>; Patrice CHOTARD - foss<patrice.chotard@foss.st.com>; Patrick DELAUNAY - foss<patrick.delaunay@foss.st.com>; Ramon Fried<rfried.dev@gmail.com>;u-boot@dh-electronics.com;uboot-stm32@st-md-mailman.stormreply.com
> Subject: [PATCH v2 09/11] net: dwc_eth_qos: Add DT parsing for STM32MP13xx platform
>
> From: Christophe Roullier<christophe.roullier@st.com>
>
> Manage 2 ethernet instances, select which instance to configure with mask If mask is not present in DT, it is stm32mp15 platform.
>
> Signed-off-by: Christophe Roullier<christophe.roullier@st.com>
> Signed-off-by: Marek Vasut<marex@denx.de>  # Rework the code
> ---
> Cc: Christophe Roullier<christophe.roullier@st.com>
> Cc: Joe Hershberger<joe.hershberger@ni.com>
> Cc: Patrice Chotard<patrice.chotard@foss.st.com>
> Cc: Patrick Delaunay<patrick.delaunay@foss.st.com>
> Cc: Ramon Fried<rfried.dev@gmail.com>
> Cc:u-boot@dh-electronics.com
> Cc:uboot-stm32@st-md-mailman.stormreply.com
> ---
> V2: - Drop unrelated clock frequency validation
>      - Move "st,ext-phyclk" property support into separate patch
>      - This leaves only the regmap parts here
> ---
>   drivers/net/dwc_eth_qos_stm32.c | 41 ++++++++++++++++++++++-----------
>   1 file changed, 28 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index 0b13d01346b..5a20fe5bea2 100644
> --- a/drivers/net/dwc_eth_qos_stm32.c
> +++ b/drivers/net/dwc_eth_qos_stm32.c
> @@ -23,6 +23,7 @@
>   #include <net.h>
>   #include <netdev.h>
>   #include <phy.h>
> +#include <regmap.h>
>   #include <reset.h>
>   #include <syscon.h>
>   #include <wait_bit.h>
> @@ -33,11 +34,16 @@
>
>   /* SYSCFG registers */
>   #define SYSCFG_PMCSETR         0x04
> -#define SYSCFG_PMCCLRR         0x44
> +#define SYSCFG_PMCCLRR_MP13    0x08
> +#define SYSCFG_PMCCLRR_MP15    0x44
> +
> +#define SYSCFG_PMCSETR_ETH1_MASK       GENMASK(23, 16)
> +#define SYSCFG_PMCSETR_ETH2_MASK       GENMASK(31, 24)
>
>   #define SYSCFG_PMCSETR_ETH_CLK_SEL     BIT(16)
>   #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
>
> +/* STM32MP15xx specific bit */
>   #define SYSCFG_PMCSETR_ETH_SELMII      BIT(20)
>
>   #define SYSCFG_PMCSETR_ETH_SEL_MASK    GENMASK(23, 21)
> @@ -130,23 +136,30 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,  {
>          /* Ethernet 50MHz RMII clock selection. */
>          const bool eth_ref_clk_sel = dev_read_bool(dev, "st,eth-ref-clk-sel");
> +       /* SoC is STM32MP13xx with two ethernet MACs */
> +       const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac");
>          /* Gigabit Ethernet 125MHz clock selection. */
>          const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
> -       u8 *syscfg;
> +       struct regmap *regmap;
> +       u32 regmap_mask;
>          u32 value;
>
> -       syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
> -       if (!syscfg)
> -               return -ENODEV;
> +       regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon");
> +       if (IS_ERR(regmap))
> +               return PTR_ERR(regmap);
> +
> +       regmap_mask = dev_read_u32_index_default(dev, "st,syscon", 2,
> +                                                SYSCFG_PMCSETR_ETH1_MASK);
>
>          switch (interface_type) {
>          case PHY_INTERFACE_MODE_MII:
>                  dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>                                     SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
> -               value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
> +               if (!is_mp13)   /* Select MII mode on STM32MP15xx */
> +                       value |= SYSCFG_PMCSETR_ETH_SELMII;
>                  break;
> -       case PHY_INTERFACE_MODE_GMII:
> +       case PHY_INTERFACE_MODE_GMII:   /* STM32MP15xx only */
>                  dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>                                     SYSCFG_PMCSETR_ETH_SEL_GMII_MII); @@ -177,13 +190,15 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>                  return -EINVAL;
>          }
>
> -       /* clear and set ETH configuration bits */
> -       writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
> -              SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
> -              syscfg + SYSCFG_PMCCLRR);
> -       writel(value, syscfg + SYSCFG_PMCSETR);
> +       /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
> +       value <<= ffs(regmap_mask) - ffs(SYSCFG_PMCSETR_ETH1_MASK);
>
> -       return 0;
> +       /* Update PMCCLRR (clear register) */
> +       regmap_write(regmap, is_mp13 ?
> +                            SYSCFG_PMCCLRR_MP13 : SYSCFG_PMCCLRR_MP15,
> +                            regmap_mask);
> +
> +       return regmap_update_bits(regmap, SYSCFG_PMCSETR, regmap_mask, value);
>   }
>
>   static int eqos_probe_resources_stm32(struct udevice *dev)
> --
> 2.43.0
Reviewed-by: Christophe ROULLIER <christophe.roullier@foss.st.com>
Patrice CHOTARD April 19, 2024, 12:11 p.m. UTC | #2 
On 4/8/24 17:50, Christophe ROULLIER wrote:
>> -----Original Message-----
>> From: Marek Vasut<marex@denx.de>
>> Sent: Tuesday, March 26, 2024 1:08 PM
>> To:u-boot@lists.denx.de
>> Cc: Christophe ROULLIER<christophe.roullier@st.com>; Marek Vasut<marex@denx.de>; Joe Hershberger<joe.hershberger@ni.com>; Patrice CHOTARD - foss<patrice.chotard@foss.st.com>; Patrick DELAUNAY - foss<patrick.delaunay@foss.st.com>; Ramon Fried<rfried.dev@gmail.com>;u-boot@dh-electronics.com;uboot-stm32@st-md-mailman.stormreply.com
>> Subject: [PATCH v2 09/11] net: dwc_eth_qos: Add DT parsing for STM32MP13xx platform
>>
>> From: Christophe Roullier<christophe.roullier@st.com>
>>
>> Manage 2 ethernet instances, select which instance to configure with mask If mask is not present in DT, it is stm32mp15 platform.
>>
>> Signed-off-by: Christophe Roullier<christophe.roullier@st.com>
>> Signed-off-by: Marek Vasut<marex@denx.de>  # Rework the code
>> ---
>> Cc: Christophe Roullier<christophe.roullier@st.com>
>> Cc: Joe Hershberger<joe.hershberger@ni.com>
>> Cc: Patrice Chotard<patrice.chotard@foss.st.com>
>> Cc: Patrick Delaunay<patrick.delaunay@foss.st.com>
>> Cc: Ramon Fried<rfried.dev@gmail.com>
>> Cc:u-boot@dh-electronics.com
>> Cc:uboot-stm32@st-md-mailman.stormreply.com
>> ---
>> V2: - Drop unrelated clock frequency validation
>>      - Move "st,ext-phyclk" property support into separate patch
>>      - This leaves only the regmap parts here
>> ---
>>   drivers/net/dwc_eth_qos_stm32.c | 41 ++++++++++++++++++++++-----------
>>   1 file changed, 28 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index 0b13d01346b..5a20fe5bea2 100644
>> --- a/drivers/net/dwc_eth_qos_stm32.c
>> +++ b/drivers/net/dwc_eth_qos_stm32.c
>> @@ -23,6 +23,7 @@
>>   #include <net.h>
>>   #include <netdev.h>
>>   #include <phy.h>
>> +#include <regmap.h>
>>   #include <reset.h>
>>   #include <syscon.h>
>>   #include <wait_bit.h>
>> @@ -33,11 +34,16 @@
>>
>>   /* SYSCFG registers */
>>   #define SYSCFG_PMCSETR         0x04
>> -#define SYSCFG_PMCCLRR         0x44
>> +#define SYSCFG_PMCCLRR_MP13    0x08
>> +#define SYSCFG_PMCCLRR_MP15    0x44
>> +
>> +#define SYSCFG_PMCSETR_ETH1_MASK       GENMASK(23, 16)
>> +#define SYSCFG_PMCSETR_ETH2_MASK       GENMASK(31, 24)
>>
>>   #define SYSCFG_PMCSETR_ETH_CLK_SEL     BIT(16)
>>   #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
>>
>> +/* STM32MP15xx specific bit */
>>   #define SYSCFG_PMCSETR_ETH_SELMII      BIT(20)
>>
>>   #define SYSCFG_PMCSETR_ETH_SEL_MASK    GENMASK(23, 21)
>> @@ -130,23 +136,30 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,  {
>>          /* Ethernet 50MHz RMII clock selection. */
>>          const bool eth_ref_clk_sel = dev_read_bool(dev, "st,eth-ref-clk-sel");
>> +       /* SoC is STM32MP13xx with two ethernet MACs */
>> +       const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac");
>>          /* Gigabit Ethernet 125MHz clock selection. */
>>          const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
>> -       u8 *syscfg;
>> +       struct regmap *regmap;
>> +       u32 regmap_mask;
>>          u32 value;
>>
>> -       syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
>> -       if (!syscfg)
>> -               return -ENODEV;
>> +       regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon");
>> +       if (IS_ERR(regmap))
>> +               return PTR_ERR(regmap);
>> +
>> +       regmap_mask = dev_read_u32_index_default(dev, "st,syscon", 2,
>> +                                                SYSCFG_PMCSETR_ETH1_MASK);
>>
>>          switch (interface_type) {
>>          case PHY_INTERFACE_MODE_MII:
>>                  dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
>>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>>                                     SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
>> -               value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
>> +               if (!is_mp13)   /* Select MII mode on STM32MP15xx */
>> +                       value |= SYSCFG_PMCSETR_ETH_SELMII;
>>                  break;
>> -       case PHY_INTERFACE_MODE_GMII:
>> +       case PHY_INTERFACE_MODE_GMII:   /* STM32MP15xx only */
>>                  dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
>>                  value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
>>                                     SYSCFG_PMCSETR_ETH_SEL_GMII_MII); @@ -177,13 +190,15 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,
>>                  return -EINVAL;
>>          }
>>
>> -       /* clear and set ETH configuration bits */
>> -       writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
>> -              SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
>> -              syscfg + SYSCFG_PMCCLRR);
>> -       writel(value, syscfg + SYSCFG_PMCSETR);
>> +       /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
>> +       value <<= ffs(regmap_mask) - ffs(SYSCFG_PMCSETR_ETH1_MASK);
>>
>> -       return 0;
>> +       /* Update PMCCLRR (clear register) */
>> +       regmap_write(regmap, is_mp13 ?
>> +                            SYSCFG_PMCCLRR_MP13 : SYSCFG_PMCCLRR_MP15,
>> +                            regmap_mask);
>> +
>> +       return regmap_update_bits(regmap, SYSCFG_PMCSETR, regmap_mask, value);
>>   }
>>
>>   static int eqos_probe_resources_stm32(struct udevice *dev)
>> -- 
>> 2.43.0
> Reviewed-by: Christophe ROULLIER <christophe.roullier@foss.st.com>

Applied on u-boot-stm32/master
diff mbox series

Patch

diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
index 0b13d01346b..5a20fe5bea2 100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -23,6 +23,7 @@ 
 #include <net.h>
 #include <netdev.h>
 #include <phy.h>
+#include <regmap.h>
 #include <reset.h>
 #include <syscon.h>
 #include <wait_bit.h>
@@ -33,11 +34,16 @@ 
 
 /* SYSCFG registers */
 #define SYSCFG_PMCSETR		0x04
-#define SYSCFG_PMCCLRR		0x44
+#define SYSCFG_PMCCLRR_MP13	0x08
+#define SYSCFG_PMCCLRR_MP15	0x44
+
+#define SYSCFG_PMCSETR_ETH1_MASK	GENMASK(23, 16)
+#define SYSCFG_PMCSETR_ETH2_MASK	GENMASK(31, 24)
 
 #define SYSCFG_PMCSETR_ETH_CLK_SEL	BIT(16)
 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL	BIT(17)
 
+/* STM32MP15xx specific bit */
 #define SYSCFG_PMCSETR_ETH_SELMII	BIT(20)
 
 #define SYSCFG_PMCSETR_ETH_SEL_MASK	GENMASK(23, 21)
@@ -130,23 +136,30 @@  static int eqos_probe_syscfg_stm32(struct udevice *dev,
 {
 	/* Ethernet 50MHz RMII clock selection. */
 	const bool eth_ref_clk_sel = dev_read_bool(dev, "st,eth-ref-clk-sel");
+	/* SoC is STM32MP13xx with two ethernet MACs */
+	const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac");
 	/* Gigabit Ethernet 125MHz clock selection. */
 	const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel");
-	u8 *syscfg;
+	struct regmap *regmap;
+	u32 regmap_mask;
 	u32 value;
 
-	syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
-	if (!syscfg)
-		return -ENODEV;
+	regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon");
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	regmap_mask = dev_read_u32_index_default(dev, "st,syscon", 2,
+						 SYSCFG_PMCSETR_ETH1_MASK);
 
 	switch (interface_type) {
 	case PHY_INTERFACE_MODE_MII:
 		dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n");
 		value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 				   SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
-		value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
+		if (!is_mp13)	/* Select MII mode on STM32MP15xx */
+			value |= SYSCFG_PMCSETR_ETH_SELMII;
 		break;
-	case PHY_INTERFACE_MODE_GMII:
+	case PHY_INTERFACE_MODE_GMII:	/* STM32MP15xx only */
 		dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n");
 		value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
 				   SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
@@ -177,13 +190,15 @@  static int eqos_probe_syscfg_stm32(struct udevice *dev,
 		return -EINVAL;
 	}
 
-	/* clear and set ETH configuration bits */
-	writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
-	       SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
-	       syscfg + SYSCFG_PMCCLRR);
-	writel(value, syscfg + SYSCFG_PMCSETR);
+	/* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
+	value <<= ffs(regmap_mask) - ffs(SYSCFG_PMCSETR_ETH1_MASK);
 
-	return 0;
+	/* Update PMCCLRR (clear register) */
+	regmap_write(regmap, is_mp13 ?
+			     SYSCFG_PMCCLRR_MP13 : SYSCFG_PMCCLRR_MP15,
+			     regmap_mask);
+
+	return regmap_update_bits(regmap, SYSCFG_PMCSETR, regmap_mask, value);
 }
 
 static int eqos_probe_resources_stm32(struct udevice *dev)