diff mbox series

drivers: spi: omap3_spi: Initialize mode for all channels

Message ID 20230526-omap3-spi-cs-fix-v1-1-dedb9081d574@baylibre.com
State Accepted
Commit fb93bd8d264c3198f321dc23a83559fcfcc275d4
Delegated to: Tom Rini
Headers show
Series drivers: spi: omap3_spi: Initialize mode for all channels | expand

Commit Message

Julien Panis May 29, 2023, 1:42 p.m. UTC 
At first SPI transfers, multiple chip selects can be
enabled simultaneously. This is due to chip select
polarity, which is not properly initialized for all
channels. This patch fixes the issue.

Signed-off-by: Julien Panis <jpanis@baylibre.com>
---
Using TI OMAP3 McSPI driver, multiple chip selects
can be enabled simultaneously during SPI transfers.
This patch fixes the issue.
---
 drivers/spi/omap3_spi.c | 20 ++++++++++++++------
 include/omap3_spi.h     |  4 +++-
 2 files changed, 17 insertions(+), 7 deletions(-)


---
base-commit: f1d33a44ca04fdca241c1d89fd79e2e56c930c7e
change-id: 20230526-omap3-spi-cs-fix-948591265425

Best regards,

Comments

Tom Rini June 21, 2023, 6:40 p.m. UTC | #1 
On Mon, May 29, 2023 at 03:42:28PM +0200, Julien Panis wrote:

> At first SPI transfers, multiple chip selects can be
> enabled simultaneously. This is due to chip select
> polarity, which is not properly initialized for all
> channels. This patch fixes the issue.
> 
> Signed-off-by: Julien Panis <jpanis@baylibre.com>

Applied to u-boot/next, thanks!
diff mbox series

Patch

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 1cbb5d46fd60..ff7b55f8707e 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -347,20 +347,28 @@  static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
 	omap3_spi_write_chconf(priv, confr);
 }
 
-static void spi_reset(struct mcspi *regs)
+static void spi_reset(struct omap3_spi_priv *priv)
 {
 	unsigned int tmp;
 
-	writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &regs->sysconfig);
+	writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &priv->regs->sysconfig);
 	do {
-		tmp = readl(&regs->sysstatus);
+		tmp = readl(&priv->regs->sysstatus);
 	} while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
 
 	writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
 	       OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
-	       OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &regs->sysconfig);
+	       OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &priv->regs->sysconfig);
 
-	writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &regs->wakeupenable);
+	writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &priv->regs->wakeupenable);
+
+	/*
+	 * Set the same default mode for each channel, especially CS polarity
+	 * which must be common for all SPI slaves before any transfer.
+	 */
+	for (priv->cs = 0 ; priv->cs < OMAP4_MCSPI_CHAN_NB ; priv->cs++)
+		_omap3_spi_set_mode(priv);
+	priv->cs = 0;
 }
 
 static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
@@ -430,7 +438,7 @@  static int omap3_spi_probe(struct udevice *dev)
 	priv->pin_dir = plat->pin_dir;
 	priv->wordlen = SPI_DEFAULT_WORDLEN;
 
-	spi_reset(priv->regs);
+	spi_reset(priv);
 
 	return 0;
 }
diff --git a/include/omap3_spi.h b/include/omap3_spi.h
index cae37705830a..5381431d4389 100644
--- a/include/omap3_spi.h
+++ b/include/omap3_spi.h
@@ -46,6 +46,8 @@ 
 
 #define OMAP4_MCSPI_REG_OFFSET	0x100
 
+#define OMAP4_MCSPI_CHAN_NB	4
+
 /* OMAP3 McSPI registers */
 struct mcspi_channel {
 	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
@@ -64,7 +66,7 @@  struct mcspi {
 	unsigned int wakeupenable;	/* 0x20 */
 	unsigned int syst;		/* 0x24 */
 	unsigned int modulctrl;		/* 0x28 */
-	struct mcspi_channel channel[4];
+	struct mcspi_channel channel[OMAP4_MCSPI_CHAN_NB];
 	/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
 	/* channel1: 0x40 - 0x50, bus 0 & 1 */
 	/* channel2: 0x54 - 0x64, bus 0 & 1 */