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[84.102.31.29]) by smtp.gmail.com with ESMTPSA id q25-20020a7bce99000000b003f4268f51f5sm14431213wmj.0.2023.05.29.06.42.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 06:43:00 -0700 (PDT) From: Julien Panis Date: Mon, 29 May 2023 15:42:28 +0200 Subject: [PATCH] drivers: spi: omap3_spi: Initialize mode for all channels MIME-Version: 1.0 Message-Id: <20230526-omap3-spi-cs-fix-v1-1-dedb9081d574@baylibre.com> X-B4-Tracking: v=1; b=H4sIAMOrdGQC/x2NQQqEMAxFryJZG9BoRecq4qJ2MprF1NKICNK7W 12+x3/8C5SjsMKnuCDyISqbz1CXBbjV+oVRvpmBKmoqQx1ufxsa1CDoFH9y4tD2ZqipMy0ZyNl slXGO1rv1CT2f+6ND5Lx+n8YppRtrZoApeQAAAA== To: Jagan Teki Cc: u-boot@lists.denx.de, vigneshr@ti.com, Julien Panis X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685367779; l=3044; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=Wju0V8nBgBIHW8ZXyl4a2Msf4POhIbM/Mz3ijk3viGI=; b=Unm8REDN9A08sYDr2t6/L7JlVN2FT8XmzYLaRNbkbQr/WWr4/SHmQV57yg9lwdg77WWOM6Yut a+mSQhQEjJFDRLyyOzPdsXwYPvXhGo1qLjuqjrMDrZntJ4tjzuiGZre X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= X-Mailman-Approved-At: Mon, 29 May 2023 15:58:35 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean At first SPI transfers, multiple chip selects can be enabled simultaneously. This is due to chip select polarity, which is not properly initialized for all channels. This patch fixes the issue. Signed-off-by: Julien Panis --- Using TI OMAP3 McSPI driver, multiple chip selects can be enabled simultaneously during SPI transfers. This patch fixes the issue. --- drivers/spi/omap3_spi.c | 20 ++++++++++++++------ include/omap3_spi.h | 4 +++- 2 files changed, 17 insertions(+), 7 deletions(-) --- base-commit: f1d33a44ca04fdca241c1d89fd79e2e56c930c7e change-id: 20230526-omap3-spi-cs-fix-948591265425 Best regards, diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 1cbb5d46fd60..ff7b55f8707e 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -347,20 +347,28 @@ static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv) omap3_spi_write_chconf(priv, confr); } -static void spi_reset(struct mcspi *regs) +static void spi_reset(struct omap3_spi_priv *priv) { unsigned int tmp; - writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig); + writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &priv->regs->sysconfig); do { - tmp = readl(®s->sysstatus); + tmp = readl(&priv->regs->sysstatus); } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE)); writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE | OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP | - OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig); + OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &priv->regs->sysconfig); - writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable); + writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &priv->regs->wakeupenable); + + /* + * Set the same default mode for each channel, especially CS polarity + * which must be common for all SPI slaves before any transfer. + */ + for (priv->cs = 0 ; priv->cs < OMAP4_MCSPI_CHAN_NB ; priv->cs++) + _omap3_spi_set_mode(priv); + priv->cs = 0; } static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) @@ -430,7 +438,7 @@ static int omap3_spi_probe(struct udevice *dev) priv->pin_dir = plat->pin_dir; priv->wordlen = SPI_DEFAULT_WORDLEN; - spi_reset(priv->regs); + spi_reset(priv); return 0; } diff --git a/include/omap3_spi.h b/include/omap3_spi.h index cae37705830a..5381431d4389 100644 --- a/include/omap3_spi.h +++ b/include/omap3_spi.h @@ -46,6 +46,8 @@ #define OMAP4_MCSPI_REG_OFFSET 0x100 +#define OMAP4_MCSPI_CHAN_NB 4 + /* OMAP3 McSPI registers */ struct mcspi_channel { unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ @@ -64,7 +66,7 @@ struct mcspi { unsigned int wakeupenable; /* 0x20 */ unsigned int syst; /* 0x24 */ unsigned int modulctrl; /* 0x28 */ - struct mcspi_channel channel[4]; + struct mcspi_channel channel[OMAP4_MCSPI_CHAN_NB]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ /* channel1: 0x40 - 0x50, bus 0 & 1 */ /* channel2: 0x54 - 0x64, bus 0 & 1 */