diff mbox series

[1/7] sunxi: SPI: fix pinmuxing for Allwinner H6 SoCs

Message ID 20220111124607.863952-2-andre.przywara@arm.com
State Accepted
Commit b106a14e2f5dfac53d9cd64a11875c011628558d
Delegated to: Andre Przywara
Headers show
Series sunxi: Fix U-Boot proper SPI operation | expand

Commit Message

Andre Przywara Jan. 11, 2022, 12:46 p.m. UTC 
From: Daniel Wagenknecht <dwagenk@mailbox.org>

The driver for SPI0 on Allwinner H6 SoCs did not use the correct define
SUN50I_GPC_SPI0 for the pin function, but one for a different Allwinner
SoC series.

Fix the conditionals to use the correct define for H6 SoCs. This matches
the conditional logic in the SPL spi driver.

Tested by probing the spi-flash on a pine64_h64-model-b board with
adapted device-tree (disable mmc2, enable spi0).

Signed-off-by: Daniel Wagenknecht <dwagenk@mailbox.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/spi/spi-sunxi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index bc2f544e86..d62355ec6f 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -249,7 +249,8 @@  static int sun4i_spi_parse_pins(struct udevice *dev)
 			if (pin < 0)
 				break;
 
-			if (IS_ENABLED(CONFIG_MACH_SUN50I))
+			if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
+			    IS_ENABLED(CONFIG_SUN50I_GEN_H6))
 				sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
 			else
 				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);