Message ID | 20210707125804.3010652-5-t.remmet@phytec.de |
---|---|
State | Accepted |
Commit | 1feac813fe54ff6466ea2d575960bc1de45b0e5c |
Delegated to: | Stefano Babic |
Headers | show |
Series | phyCORE-i.MX8MP Update | expand |
> With the first redesign the debug UART had changed from > UART2 to UART1. > As the first hardware revision is considered as alpha and > will not be supported in future. The old setup will not > be preserved. > Signed-off-by: Teresa Remmet <t.remmet@phytec.de> > Reviewed-by: Fabio Estevam <festevam@gmail.com> > Reviewed-by: Heiko Schocher <hs@denx.de> Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic
> With the first redesign the debug UART had changed from > UART2 to UART1. > As the first hardware revision is considered as alpha and > will not be supported in future. The old setup will not > be preserved. > Signed-off-by: Teresa Remmet <t.remmet@phytec.de> > Reviewed-by: Fabio Estevam <festevam@gmail.com> > Reviewed-by: Heiko Schocher <hs@denx.de> Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index 6c1528934a98..32ed037e3721 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -18,7 +18,7 @@ u-boot,dm-spl; }; -&pinctrl_uart2 { +&pinctrl_uart1 { u-boot,dm-spl; }; @@ -54,7 +54,7 @@ u-boot,dm-spl; }; -&uart2 { +&uart1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts index 2031a9d40bed..984a6b9ded8d 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts @@ -16,7 +16,7 @@ "phytec,imx8mp-phycore-som", "fsl,imx8mp"; chosen { - stdout-path = &uart2; + stdout-path = &uart1; }; reg_usdhc2_vmmc: regulator-usdhc2 { @@ -95,9 +95,9 @@ }; /* debug console */ -&uart2 { +&uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; @@ -154,10 +154,10 @@ >; }; - pinctrl_uart2: uart2grp { + pinctrl_uart1: uart1grp { fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49 >; }; diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index f9fa8d1e1281..0bc4c7693b06 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -80,8 +80,8 @@ int board_fit_config_name_match(const char *name) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) static iomux_v3_cfg_t const uart_pads[] = { - MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const wdog_pads[] = { @@ -107,7 +107,7 @@ void board_init_f(ulong dummy) arch_cpu_init(); - init_uart_clk(1); + init_uart_clk(0); board_early_init_f(); diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 04900498507a..e24f223c21d3 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -39,7 +39,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ - "console=ttymxc1,115200\0" \ + "console=ttymxc0,115200\0" \ "fdt_addr=0x48000000\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ @@ -87,7 +87,7 @@ #define PHYS_SDRAM_SIZE 0x80000000 /* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K