Message ID | 20210707125804.3010652-8-t.remmet@phytec.de |
---|---|
State | Accepted |
Commit | fd82763cd256a0470d85a00458735721db719a00 |
Delegated to: | Stefano Babic |
Headers | show |
Series | phyCORE-i.MX8MP Update | expand |
> Enable DVS1 control through PMIC_STBY_REQ. > Signed-off-by: Teresa Remmet <t.remmet@phytec.de> > Reviewed-by: Fabio Estevam <festevam@gmail.com> Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic
> Enable DVS1 control through PMIC_STBY_REQ. > Signed-off-by: Teresa Remmet <t.remmet@phytec.de> > Reviewed-by: Fabio Estevam <festevam@gmail.com> Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 815ca9badcba..19c486e55174 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -66,7 +66,11 @@ int power_init_board(void) pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); - /* set WDOG_B_CFG to cold reset */ + /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set WDOG_B_CFG to cold reset */ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); return 0;