| Message ID | 20210407043228.2268429-4-sjg@chromium.org |
|---|---|
| State | Superseded |
| Delegated to: | Bin Meng |
| Headers | show |
| Series | misc: Some more misc patches | expand |
On Wed, Apr 7, 2021 at 12:34 PM Simon Glass <sjg@chromium.org> wrote: > > When booting from coreboot we may not have a PCH driver available. The > SPI driver can operate without the PCH but currently complains in this > case. Update it to continue to work normally. The only missing feature > is memory-mapping of SPI-flash contents, which is not essential. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > drivers/spi/ich.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> But I feel this driver is slightly becoming unmaintainable as there are many combinations we need to consider ... Regards, Bin
Hi Bin, On Thu, 8 Apr 2021 at 14:28, Bin Meng <bmeng.cn@gmail.com> wrote: > > On Wed, Apr 7, 2021 at 12:34 PM Simon Glass <sjg@chromium.org> wrote: > > > > When booting from coreboot we may not have a PCH driver available. The > > SPI driver can operate without the PCH but currently complains in this > > case. Update it to continue to work normally. The only missing feature > > is memory-mapping of SPI-flash contents, which is not essential. > > > > Signed-off-by: Simon Glass <sjg@chromium.org> > > --- > > > > drivers/spi/ich.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > But I feel this driver is slightly becoming unmaintainable as there > are many combinations we need to consider ... Yes it is a bit of a pain. The main one is that in some cases the SPI bus appears on PCI and in others it is part of the PCH or LPC. This is a hardware thing though, so I'm not sure what we can do about it. Perhaps split up the driver? Regards, Simon
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 1cd410493b0..3d49c22a9da 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -114,7 +114,7 @@ static bool ich9_can_do_33mhz(struct udevice *dev) struct ich_spi_priv *priv = dev_get_priv(dev); u32 fdod, speed; - if (!CONFIG_IS_ENABLED(PCI)) + if (!CONFIG_IS_ENABLED(PCI) || !priv->pch) return false; /* Observe SPI Descriptor Component Section 0 */ dm_pci_write_config32(priv->pch, 0xb0, 0x1000); @@ -632,7 +632,7 @@ static int ich_spi_get_basics(struct udevice *bus, bool can_probe, if (device_get_uclass_id(pch) != UCLASS_PCH) { uclass_first_device(UCLASS_PCH, &pch); if (!pch) - return log_msg_ret("uclass", -EPROTOTYPE); + ; /* ignore this error since we don't need it */ } }
When booting from coreboot we may not have a PCH driver available. The SPI driver can operate without the PCH but currently complains in this case. Update it to continue to work normally. The only missing feature is memory-mapping of SPI-flash contents, which is not essential. Signed-off-by: Simon Glass <sjg@chromium.org> --- drivers/spi/ich.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)