| Message ID | 20210331143908.48211-17-elly.siew.chin.lim@intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | Add Intel N5X SoC support | expand |
> -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > Sent: Wednesday, March 31, 2021 10:39 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin.lim@intel.com> > Subject: [v1 16/17] include: configs: Add Intel N5X device CONFIGs > > Add CONFIGs for N5X. > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> > --- > include/configs/socfpga_n5x_socdk.h | 45 > +++++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > create mode 100644 include/configs/socfpga_n5x_socdk.h > > diff --git a/include/configs/socfpga_n5x_socdk.h > b/include/configs/socfpga_n5x_socdk.h > new file mode 100644 > index 0000000000..c295e91e3d > --- /dev/null > +++ b/include/configs/socfpga_n5x_socdk.h > @@ -0,0 +1,45 @@ > +/* SPDX-License-Identifier: GPL-2.0 > + * > + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> > + * > + */ > + > +#ifndef __CONFIG_SOCFGPA_N5X_H__ > +#define __CONFIG_SOCFGPA_N5X_H__ > + > +#include <configs/socfpga_soc64_common.h> > + > +#undef CONFIG_EXTRA_ENV_SETTINGS > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > + "bootfile=" CONFIG_BOOTFILE "\0" \ > + "fdt_addr=1100000\0" \ > + "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ > + "mmcroot=/dev/mmcblk0p2\0" \ > + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ > + " root=${mmcroot} rw rootwait;" \ > + "booti ${loadaddr} - ${fdt_addr}\0" \ > + "mmcload=mmc rescan;" \ > + "load mmc 0:1 ${loadaddr} ${bootfile};" \ > + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ > + "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \ > + " root=${mmcroot} rw rootwait;" \ > + "bootm ${loadaddr}\0" \ > + "mmcfitload=mmc rescan;" \ > + "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ > + "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \ > + "booti ${loadaddr} - ${fdt_addr}\0" \ > + "linux_qspi_enable=if sf probe; then " \ > + "echo Enabling QSPI at Linux DTB...;" \ > + "fdt addr ${fdt_addr}; fdt resize;" \ > + "fdt set /soc/spi@ff8d2000 status okay;" \ > + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ > + " ${qspi_clock}; then" \ > + " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ > + " ${qspi_clock}; fi; fi\0" \ > + "scriptaddr=0x02100000\0" \ > + "scriptfile=u-boot.scr\0" \ > + "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ > + "then source ${scriptaddr}; fi\0" > + > +#endif /* __CONFIG_SOCFGPA_N5X_H__ */ > -- Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff --git a/include/configs/socfpga_n5x_socdk.h b/include/configs/socfpga_n5x_socdk.h new file mode 100644 index 0000000000..c295e91e3d --- /dev/null +++ b/include/configs/socfpga_n5x_socdk.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + * + */ + +#ifndef __CONFIG_SOCFGPA_N5X_H__ +#define __CONFIG_SOCFGPA_N5X_H__ + +#include <configs/socfpga_soc64_common.h> + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ + "fdt_addr=1100000\0" \ + "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootm ${loadaddr}\0" \ + "mmcfitload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then" \ + " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; fi; fi\0" \ + "scriptaddr=0x02100000\0" \ + "scriptfile=u-boot.scr\0" \ + "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ + "then source ${scriptaddr}; fi\0" + +#endif /* __CONFIG_SOCFGPA_N5X_H__ */
Add CONFIGs for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> --- include/configs/socfpga_n5x_socdk.h | 45 +++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/configs/socfpga_n5x_socdk.h