diff mbox series

[02/26] imx8mm_evk: Update to latest LPDDR4 script

Message ID 20210319075718.14181-3-peng.fan@oss.nxp.com
State Accepted
Commit cf16dc3329bd396e624cddaf35ef5c1bf77da66c
Delegated to: Stefano Babic
Headers show
Series imx: update for i.MX8M | expand

Commit Message

Peng Fan (OSS) March 19, 2021, 7:56 a.m. UTC 
From: Ye Li <ye.li@nxp.com>

Update LPDDR4 script to sync with v2020.04 u-boot

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 board/freescale/imx8mm_evk/lpddr4_timing.c | 692 +++++++++------------
 1 file changed, 280 insertions(+), 412 deletions(-)

Comments

Tim Harvey March 24, 2021, 9:19 p.m. UTC | #1 
On Fri, Mar 19, 2021 at 12:26 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Ye Li <ye.li@nxp.com>
>
> Update LPDDR4 script to sync with v2020.04 u-boot
>
> Signed-off-by: Ye Li <ye.li@nxp.com>

Peng,

The commit log does not make sense. I believe you want to say
something like 'Update LPDDR4 script to sync with <xyz> version of the
NXP MX8M_DDR_tool'.

> ---
>  board/freescale/imx8mm_evk/lpddr4_timing.c | 692 +++++++++------------
>  1 file changed, 280 insertions(+), 412 deletions(-)
>
> diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c
> index 8e48b9d81b..4373ca624e 100644
> --- a/board/freescale/imx8mm_evk/lpddr4_timing.c
> +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> @@ -1,129 +1,162 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
> - * Copyright 2019 NXP
> + * Copyright 2018-2019 NXP
> + *
> + * Generated code from MX8M_DDR_tool
>   */

I understand that this file is a direct output of the NXP MX8M_DDR
tool but it would be nice to see you add to the comment above what
version of the tool you used to produce this what functional
differences it makes. If you knew what version of the tool produced
the original file one could compare versions.

As I am the maintainer of an IMX8M Mini board also, I try to pay
attention to NXP's updates to the DDR timing config files to let me
know if something important has changed.

Best Regards,

Tim
Peng Fan (OSS) March 25, 2021, 1:15 a.m. UTC | #2 
> Subject: Re: [PATCH 02/26] imx8mm_evk: Update to latest LPDDR4 script
> 
> On Fri, Mar 19, 2021 at 12:26 AM Peng Fan (OSS) <peng.fan@oss.nxp.com>
> wrote:
> >
> > From: Ye Li <ye.li@nxp.com>
> >
> > Update LPDDR4 script to sync with v2020.04 u-boot
> >
> > Signed-off-by: Ye Li <ye.li@nxp.com>
> 
> Peng,
> 
> The commit log does not make sense. I believe you want to say something like
> 'Update LPDDR4 script to sync with <xyz> version of the NXP
> MX8M_DDR_tool'.

I directly cherry-pick this patch from downstream tree,
Ye could comment more here.

Regards,
Peng.

> 
> > ---
> >  board/freescale/imx8mm_evk/lpddr4_timing.c | 692
> > +++++++++------------
> >  1 file changed, 280 insertions(+), 412 deletions(-)
> >
> > diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > index 8e48b9d81b..4373ca624e 100644
> > --- a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > @@ -1,129 +1,162 @@
> >  // SPDX-License-Identifier: GPL-2.0+
> >  /*
> > - * Copyright 2019 NXP
> > + * Copyright 2018-2019 NXP
> > + *
> > + * Generated code from MX8M_DDR_tool
> >   */
> 
> I understand that this file is a direct output of the NXP MX8M_DDR tool but it
> would be nice to see you add to the comment above what version of the tool
> you used to produce this what functional differences it makes. If you knew
> what version of the tool produced the original file one could compare versions.
> 
> As I am the maintainer of an IMX8M Mini board also, I try to pay attention to
> NXP's updates to the DDR timing config files to let me know if something
> important has changed.
> 
> Best Regards,
> 
> Tim
diff mbox series

Patch

diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c
index 8e48b9d81b..4373ca624e 100644
--- a/board/freescale/imx8mm_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
@@ -1,129 +1,162 @@ 
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2018-2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
  */
 
 #include <linux/kernel.h>
-#include <common.h>
 #include <asm/arch/ddr.h>
-#include <asm/arch/lpddr4_define.h>
 
-struct dram_cfg_param lpddr4_ddrc_cfg[] = {
-	/* Start to config, default 3200mbps */
-	{ DDRC_DBG1(0),	0x00000001 },
-	{ DDRC_PWRCTL(0), 0x00000001 },
-	{ DDRC_MSTR(0),	0xa1080020 },
-	{ DDRC_RFSHTMG(0), 0x005b00d2 },
-	{ DDRC_INIT0(0), 0xC003061B },
-	{ DDRC_INIT1(0), 0x009D0000 },
-	{ DDRC_INIT3(0), 0x00D4002D },
-	{ DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
-	{ DDRC_INIT6(0), 0x0066004a },
-	{ DDRC_INIT7(0), 0x0006004a },
-
-	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
-	{ DDRC_DRAMTMG1(0), 0x00060633 },
-	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
-	{ DDRC_DRAMTMG4(0), 0x0F04080F },
-	{ DDRC_DRAMTMG5(0), 0x02040C0C },
-	{ DDRC_DRAMTMG6(0), 0x01010007 },
-	{ DDRC_DRAMTMG7(0), 0x00000401 },
-	{ DDRC_DRAMTMG12(0), 0x00020600 },
-	{ DDRC_DRAMTMG13(0), 0x0C100002 },
-	{ DDRC_DRAMTMG14(0), 0x000000E6 },
-	{ DDRC_DRAMTMG17(0), 0x00A00050 },
-
-	{ DDRC_ZQCTL0(0), 0x03200018 },
-	{ DDRC_ZQCTL1(0), 0x028061A8 },
-	{ DDRC_ZQCTL2(0), 0x00000000 },
-
-	{ DDRC_DFITMG0(0), 0x0497820A },
-	{ DDRC_DFITMG2(0), 0x0000170A },
-	{ DDRC_DRAMTMG2(0), 0x070E171a },
-	{ DDRC_DBICTL(0), 0x00000001 },
-
-	{ DDRC_DFITMG1(0), 0x00080303 },
-	{ DDRC_DFIUPD0(0), 0xE0400018 },
-	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
-	{ DDRC_DFIUPD2(0), 0x80000000 },
-	{ DDRC_DFIMISC(0), 0x00000011 },
-
-	{ DDRC_DFIPHYMSTR(0), 0x00000000 },
-	{ DDRC_RANKCTL(0), 0x00000c99 },
-
-	/* address mapping */
-	{ DDRC_ADDRMAP0(0), 0x0000001f },
-	{ DDRC_ADDRMAP1(0), 0x00080808 },
-	{ DDRC_ADDRMAP2(0), 0x00000000 },
-	{ DDRC_ADDRMAP3(0), 0x00000000 },
-	{ DDRC_ADDRMAP4(0), 0x00001f1f },
-	{ DDRC_ADDRMAP5(0), 0x07070707 },
-	{ DDRC_ADDRMAP6(0), 0x07070707 },
-	{ DDRC_ADDRMAP7(0), 0x00000f0f },
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/* Initialize DDRC registers */
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x223 },
+	{ 0x3d400024, 0x16e3600 },
+	{ 0x3d400064, 0x5b00d2 },
+	{ 0x3d4000d0, 0xc00305ba },
+	{ 0x3d4000d4, 0x940000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x191e1920 },
+	{ 0x3d400104, 0x60630 },
+	{ 0x3d40010c, 0xb0b000 },
+	{ 0x3d400110, 0xe04080e },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xd8 },
+	{ 0x3d400144, 0x96004b },
+	{ 0x3d400180, 0x2ee0017 },
+	{ 0x3d400184, 0x2605b8e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
 
 	/* performance setting */
-	{ DDRC_SCHED(0), 0x29001701 },
-	{ DDRC_SCHED1(0), 0x0000002c },
-	{ DDRC_PERFHPR1(0), 0x04000030 },
-	{ DDRC_PERFLPR1(0), 0x900093e7 },
-	{ DDRC_PERFWR1(0), 0x20005574 },
-	{ DDRC_PCCFG(0), 0x00000111 },
-	{ DDRC_PCFGW_0(0), 0x000072ff },
-	{ DDRC_PCFGQOS0_0(0), 0x02100e07 },
-	{ DDRC_PCFGQOS1_0(0), 0x00620096 },
-	{ DDRC_PCFGWQOS0_0(0), 0x01100e07 },
-	{ DDRC_PCFGWQOS1_0(0), 0x00c8012c },
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
 
-	/* frequency P1&P2 */
-	/* Frequency 1: 400mbps */
-	{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
-	{ DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
-	{ DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
-	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
-	{ DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
-	{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
-	{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
-	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
-	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
-	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
-	{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
-	{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
-	{ DDRC_FREQ1_DFITMG0(0), 0x03818200 },
-	{ DDRC_FREQ1_DFITMG2(0), 0x00000000 },
-	{ DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
-	{ DDRC_FREQ1_INIT3(0), 0x00840000 },
-	{ DDRC_FREQ1_INIT4(0), 0x00310000 },
-	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
-	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
+	/* P1: 400mts */
+	{ 0x3d402020, 0x21 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
 
-	/* Frequency 2: 100mbps */
-	{ DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
-	{ DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
-	{ DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
-	{ DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
-	{ DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
-	{ DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
-	{ DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
-	{ DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
-	{ DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
-	{ DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
-	{ DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
-	{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
-	{ DDRC_FREQ2_DFITMG2(0), 0x00000000 },
-	{ DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
-	{ DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
-	{ DDRC_FREQ2_INIT3(0), 0x00840000 },
-	{ DDRC_FREQ2_INIT4(0), 0x00310008 },
-	{ DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
-	{ DDRC_FREQ2_INIT6(0), 0x0066004a },
-	{ DDRC_FREQ2_INIT7(0), 0x0006004a },
+	/* p2: 100mts */
+	{ 0x3d403020, 0x21 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
 
-	/* boot start point */
-	{ DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+	/* default boot point */
+	{ 0x3d400028, 0x0 },
 };
 
 /* PHY Initialize Configuration */
-struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
 	{ 0x1005f, 0x1ff },
 	{ 0x1015f, 0x1ff },
 	{ 0x1105f, 0x1ff },
@@ -132,7 +165,6 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x1215f, 0x1ff },
 	{ 0x1305f, 0x1ff },
 	{ 0x1315f, 0x1ff },
-
 	{ 0x11005f, 0x1ff },
 	{ 0x11015f, 0x1ff },
 	{ 0x11105f, 0x1ff },
@@ -141,7 +173,6 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x11215f, 0x1ff },
 	{ 0x11305f, 0x1ff },
 	{ 0x11315f, 0x1ff },
-
 	{ 0x21005f, 0x1ff },
 	{ 0x21015f, 0x1ff },
 	{ 0x21105f, 0x1ff },
@@ -150,7 +181,6 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x21215f, 0x1ff },
 	{ 0x21305f, 0x1ff },
 	{ 0x21315f, 0x1ff },
-
 	{ 0x55, 0x1ff },
 	{ 0x1055, 0x1ff },
 	{ 0x2055, 0x1ff },
@@ -161,32 +191,24 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x7055, 0x1ff },
 	{ 0x8055, 0x1ff },
 	{ 0x9055, 0x1ff },
-
 	{ 0x200c5, 0x19 },
 	{ 0x1200c5, 0x7 },
 	{ 0x2200c5, 0x7 },
-
 	{ 0x2002e, 0x2 },
 	{ 0x12002e, 0x2 },
 	{ 0x22002e, 0x2 },
-
 	{ 0x90204, 0x0 },
 	{ 0x190204, 0x0 },
 	{ 0x290204, 0x0 },
-
-	{ 0x20024, 0xab },
+	{ 0x20024, 0x1ab },
 	{ 0x2003a, 0x0 },
-
-	{ 0x120024, 0xab },
+	{ 0x120024, 0x1ab },
 	{ 0x2003a, 0x0 },
-
-	{ 0x220024, 0xab },
+	{ 0x220024, 0x1ab },
 	{ 0x2003a, 0x0 },
-
 	{ 0x20056, 0x3 },
 	{ 0x120056, 0xa },
 	{ 0x220056, 0xa },
-
 	{ 0x1004d, 0xe00 },
 	{ 0x1014d, 0xe00 },
 	{ 0x1104d, 0xe00 },
@@ -195,7 +217,6 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x1214d, 0xe00 },
 	{ 0x1304d, 0xe00 },
 	{ 0x1314d, 0xe00 },
-
 	{ 0x11004d, 0xe00 },
 	{ 0x11014d, 0xe00 },
 	{ 0x11104d, 0xe00 },
@@ -204,7 +225,6 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x11214d, 0xe00 },
 	{ 0x11304d, 0xe00 },
 	{ 0x11314d, 0xe00 },
-
 	{ 0x21004d, 0xe00 },
 	{ 0x21014d, 0xe00 },
 	{ 0x21104d, 0xe00 },
@@ -213,34 +233,30 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x21214d, 0xe00 },
 	{ 0x21304d, 0xe00 },
 	{ 0x21314d, 0xe00 },
-
-	{ 0x10049, 0xfbe },
-	{ 0x10149, 0xfbe },
-	{ 0x11049, 0xfbe },
-	{ 0x11149, 0xfbe },
-	{ 0x12049, 0xfbe },
-	{ 0x12149, 0xfbe },
-	{ 0x13049, 0xfbe },
-	{ 0x13149, 0xfbe },
-
-	{ 0x110049, 0xfbe },
-	{ 0x110149, 0xfbe },
-	{ 0x111049, 0xfbe },
-	{ 0x111149, 0xfbe },
-	{ 0x112049, 0xfbe },
-	{ 0x112149, 0xfbe },
-	{ 0x113049, 0xfbe },
-	{ 0x113149, 0xfbe },
-
-	{ 0x210049, 0xfbe },
-	{ 0x210149, 0xfbe },
-	{ 0x211049, 0xfbe },
-	{ 0x211149, 0xfbe },
-	{ 0x212049, 0xfbe },
-	{ 0x212149, 0xfbe },
-	{ 0x213049, 0xfbe },
-	{ 0x213149, 0xfbe },
-
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
 	{ 0x43, 0x63 },
 	{ 0x1043, 0x63 },
 	{ 0x2043, 0x63 },
@@ -251,7 +267,6 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x7043, 0x63 },
 	{ 0x8043, 0x63 },
 	{ 0x9043, 0x63 },
-
 	{ 0x20018, 0x3 },
 	{ 0x20075, 0x4 },
 	{ 0x20050, 0x0 },
@@ -259,8 +274,7 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x120008, 0x64 },
 	{ 0x220008, 0x19 },
 	{ 0x20088, 0x9 },
-
-	{ 0x200b2, 0x1d4 },
+	{ 0x200b2, 0xdc },
 	{ 0x10043, 0x5a1 },
 	{ 0x10143, 0x5a1 },
 	{ 0x11043, 0x5a1 },
@@ -269,7 +283,6 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x12143, 0x5a1 },
 	{ 0x13043, 0x5a1 },
 	{ 0x13143, 0x5a1 },
-
 	{ 0x1200b2, 0xdc },
 	{ 0x110043, 0x5a1 },
 	{ 0x110143, 0x5a1 },
@@ -279,7 +292,6 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x112143, 0x5a1 },
 	{ 0x113043, 0x5a1 },
 	{ 0x113143, 0x5a1 },
-
 	{ 0x2200b2, 0xdc },
 	{ 0x210043, 0x5a1 },
 	{ 0x210143, 0x5a1 },
@@ -289,15 +301,12 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x212143, 0x5a1 },
 	{ 0x213043, 0x5a1 },
 	{ 0x213143, 0x5a1 },
-
 	{ 0x200fa, 0x1 },
 	{ 0x1200fa, 0x1 },
 	{ 0x2200fa, 0x1 },
-
 	{ 0x20019, 0x1 },
 	{ 0x120019, 0x1 },
 	{ 0x220019, 0x1 },
-
 	{ 0x200f0, 0x660 },
 	{ 0x200f1, 0x0 },
 	{ 0x200f2, 0x4444 },
@@ -306,21 +315,20 @@  struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x200f5, 0x0 },
 	{ 0x200f6, 0x0 },
 	{ 0x200f7, 0xf000 },
-
 	{ 0x20025, 0x0 },
-	{ 0x2002d, LPDDR4_PHY_DMIPinPresent },
-	{ 0x12002d, LPDDR4_PHY_DMIPinPresent },
-	{ 0x22002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
 	{ 0x200c7, 0x21 },
-	{ 0x200ca, 0x24 },
 	{ 0x1200c7, 0x21 },
-	{ 0x1200ca, 0x24 },
 	{ 0x2200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200ca, 0x24 },
 	{ 0x2200ca, 0x24 },
 };
 
 /* ddr phy trained csr */
-struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{ 0x200b2, 0x0 },
 	{ 0x1200b2, 0x0 },
 	{ 0x2200b2, 0x0 },
@@ -1041,309 +1049,164 @@  struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
 	{ 0x13730, 0x0 },
 	{ 0x13830, 0x0 },
 };
-
 /* P0 message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
-	{ 0x54002, 0x0 },
 	{ 0x54003, 0xbb8 },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
 	{ 0x54008, 0x131f },
 	{ 0x54009, 0xc8 },
-	{ 0x5400a, 0x0 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, 0x0 },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
-	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
+	{ 0x54012, 0x110 },
 	{ 0x54019, 0x2dd4 },
-	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401a, 0x31 },
 	{ 0x5401b, 0x4d66 },
-	{ 0x5401c, 0x4d08 },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
-	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54020, 0x31 },
 	{ 0x54021, 0x4d66 },
-	{ 0x54022, 0x4d08 },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
-	{ 0x5402c, LPDDR4_CS },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
+	{ 0x5402c, 0x1 },
 	{ 0x54032, 0xd400 },
-	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54033, 0x312d },
 	{ 0x54034, 0x6600 },
-	{ 0x54035, 0x84d },
+	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
-	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54039, 0x312d },
 	{ 0x5403a, 0x6600 },
-	{ 0x5403b, 0x84d },
+	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
 };
 
 /* P1 message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
 	{ 0x54002, 0x101 },
 	{ 0x54003, 0x190 },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
 	{ 0x54008, 0x121f },
 	{ 0x54009, 0xc8 },
-	{ 0x5400a, 0x0 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, 0x0 },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
-	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
+	{ 0x54012, 0x110 },
 	{ 0x54019, 0x84 },
-	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401a, 0x31 },
 	{ 0x5401b, 0x4d66 },
-	{ 0x5401c, 0x4d08 },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
-	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54020, 0x31 },
 	{ 0x54021, 0x4d66 },
-	{ 0x54022, 0x4d08 },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
-	{ 0x5402c, LPDDR4_CS },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
+	{ 0x5402c, 0x1 },
 	{ 0x54032, 0x8400 },
-	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54033, 0x3100 },
 	{ 0x54034, 0x6600 },
-	{ 0x54035, 0x84d },
+	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
-	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54039, 0x3100 },
 	{ 0x5403a, 0x6600 },
-	{ 0x5403b, 0x84d },
+	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
 };
 
-/* P1 message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
 	{ 0x54002, 0x102 },
 	{ 0x54003, 0x64 },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
 	{ 0x54008, 0x121f },
 	{ 0x54009, 0xc8 },
-	{ 0x5400a, 0x0 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, 0x0 },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
-	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
+	{ 0x54012, 0x110 },
 	{ 0x54019, 0x84 },
-	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401a, 0x31 },
 	{ 0x5401b, 0x4d66 },
-	{ 0x5401c, 0x4d08 },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
-	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54020, 0x31 },
 	{ 0x54021, 0x4d66 },
-	{ 0x54022, 0x4d08 },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
-	{ 0x5402c, LPDDR4_CS },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
+	{ 0x5402c, 0x1 },
 	{ 0x54032, 0x8400 },
-	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54033, 0x3100 },
 	{ 0x54034, 0x6600 },
-	{ 0x54035, 0x84d },
+	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
-	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54039, 0x3100 },
 	{ 0x5403a, 0x6600 },
-	{ 0x5403b, 0x84d },
+	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
 };
 
 /* P0 2D message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
-	{ 0x54002, 0x0 },
 	{ 0x54003, 0xbb8 },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
 	{ 0x54008, 0x61 },
 	{ 0x54009, 0xc8 },
-	{ 0x5400a, 0x0 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, 0x0 },
-	{ 0x5400e, 0x0 },
 	{ 0x5400f, 0x100 },
 	{ 0x54010, 0x1f7f },
-	{ 0x54011, 0x0 },
-	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
+	{ 0x54012, 0x110 },
 	{ 0x54019, 0x2dd4 },
-	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401a, 0x31 },
 	{ 0x5401b, 0x4d66 },
-	{ 0x5401c, 0x4d08 },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
-	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54020, 0x31 },
 	{ 0x54021, 0x4d66 },
-	{ 0x54022, 0x4d08 },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
-	{ 0x5402c, LPDDR4_CS },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
+	{ 0x5402c, 0x1 },
 	{ 0x54032, 0xd400 },
-	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54033, 0x312d },
 	{ 0x54034, 0x6600 },
-	{ 0x54035, 0x84d },
+	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
-	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54039, 0x312d },
 	{ 0x5403a, 0x6600 },
-	{ 0x5403b, 0x84d },
+	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
 };
 
 /* DRAM PHY init engine image */
-struct dram_cfg_param lpddr4_phy_pie[] = {
+struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0xd0000, 0x0 },
 	{ 0x90000, 0x10 },
 	{ 0x90001, 0x400 },
@@ -1854,6 +1717,10 @@  struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x90013, 0x6152 },
 	{ 0x20010, 0x5a },
 	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
 	{ 0x40080, 0xe0 },
 	{ 0x40081, 0x12 },
 	{ 0x40082, 0xe0 },
@@ -1931,50 +1798,51 @@  struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x138b4, 0x1 },
 	{ 0x2003a, 0x2 },
 	{ 0xc0080, 0x2 },
-	{ 0xd0000, 0x1 },
+	{ 0xd0000, 0x1 }
 };
 
-struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 	{
 		/* P0 3000mts 1D */
 		.drate = 3000,
 		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = lpddr4_fsp0_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
-	},
-	{
-		/* P0 3000mts 2D */
-		.drate = 3000,
-		.fw_type = FW_2D_IMAGE,
-		.fsp_cfg = lpddr4_fsp0_2d_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
 	},
 	{
 		/* P1 400mts 1D */
 		.drate = 400,
 		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = lpddr4_fsp1_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
 	},
 	{
-		/* P1 100mts 1D */
+		/* P2 100mts 1D */
 		.drate = 100,
 		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = lpddr4_fsp2_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
 	},
 };
 
-/* lpddr4 timing config params on EVK board */
+/* ddr timing config params */
 struct dram_timing_info dram_timing = {
-	.ddrc_cfg = lpddr4_ddrc_cfg,
-	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
-	.ddrphy_cfg = lpddr4_ddrphy_cfg,
-	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
-	.fsp_msg = lpddr4_dram_fsp_msg,
-	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
-	.ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
-	.ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
-	.ddrphy_pie = lpddr4_phy_pie,
-	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
 };