diff mbox series

[22/26] imx8m: ddr: Disable CA VREF Training for LPDDR4

Message ID 20210319075718.14181-23-peng.fan@oss.nxp.com
State Accepted
Commit 8f9f6ba85556a4ab9f1df93d85ff44ce0dbbd4fa
Delegated to: Stefano Babic
Headers show
Series imx: update for i.MX8M | expand

Commit Message

Peng Fan (OSS) March 19, 2021, 7:57 a.m. UTC 
From: Ye Li <ye.li@nxp.com>

Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
but not set in 1D.  According to PHY training application node,
to enable the feature both 1D and 2D need set this field to 1,
otherwise the training result will be incorrect.
The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
MR12 value from message block (FSP structure). So update the LPDDR4
scripts of all mscale to clear CATrainOpt[0].

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8mn_evk/lpddr4_timing_ld.c | 1 -
 board/freescale/imx8mp_evk/lpddr4_timing.c    | 2 --
 2 files changed, 3 deletions(-)

Comments

Tim Harvey March 24, 2021, 9:25 p.m. UTC | #1 
On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Ye Li <ye.li@nxp.com>
>
> Users reported LPDDR4 MR12 value is set to 0 during PHY training,
> not the value from FSP timing structure, which cause compliance test failed.
> The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
> but not set in 1D.  According to PHY training application node,
> to enable the feature both 1D and 2D need set this field to 1,
> otherwise the training result will be incorrect.
> The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
> MR12 value from message block (FSP structure). So update the LPDDR4
> scripts of all mscale to clear CATrainOpt[0].

Peng,

Is this issue being addressed by an update of the NXP i.MX 8M Family
DDR Tools app that generates this code? Is there a reference to this
issue online anywhere?

A bit unrelated but I would love to see NXP step up and replace the
silly NXP i.MX 8M Family DDR Tools windows app with code that could be
enabled in the SPL to do the same thing. Personally it's a bit of a
joke to require having a Windows PC around to bring up an ARM
processor board and I would hope there are folks at NXP that are
utterly ashamed at this as well. One could easily use the opensource
imx-usb-loader to load an SPL that performed this calibration and
training code.

Tim
Stefano Babic March 25, 2021, 8:14 a.m. UTC | #2 
Hi Tim,

On 24.03.21 22:25, Tim Harvey wrote:
> On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>>
>> From: Ye Li <ye.li@nxp.com>
>>
>> Users reported LPDDR4 MR12 value is set to 0 during PHY training,
>> not the value from FSP timing structure, which cause compliance test failed.
>> The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
>> but not set in 1D.  According to PHY training application node,
>> to enable the feature both 1D and 2D need set this field to 1,
>> otherwise the training result will be incorrect.
>> The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
>> MR12 value from message block (FSP structure). So update the LPDDR4
>> scripts of all mscale to clear CATrainOpt[0].
> 
> Peng,
> 
> Is this issue being addressed by an update of the NXP i.MX 8M Family
> DDR Tools app that generates this code? Is there a reference to this
> issue online anywhere?
> 
> A bit unrelated but I would love to see NXP step up and replace the
> silly NXP i.MX 8M Family DDR Tools windows app with code that could be
> enabled in the SPL to do the same thing. Personally it's a bit of a
> joke to require having a Windows PC around to bring up an ARM
> processor board and I would hope there are folks at NXP that are
> utterly ashamed at this as well. One could easily use the opensource
> imx-usb-loader to load an SPL that performed this calibration and
> training code.

You find a lot of friends here....most of us will frankly be glad if 
there will be such as tool, or at least if some code is published to 
help to port to Linux. NXP story did not show a big interest in the past 
with the Windows-based MFGTools, but I hoped this was changed with 
"uuu". Such as tool will really help to improve i.MX support and enlarge 
NXP community (just a couple of notes: I do not expect Peng can decide 
this, but he can report our thought internally to NXP).

Best regards,
Stefano
Peng Fan (OSS) March 25, 2021, 8:35 a.m. UTC | #3 
On 2021/3/25 16:14, Stefano Babic wrote:
> Hi Tim,
> 
> On 24.03.21 22:25, Tim Harvey wrote:
>> On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> 
>> wrote:
>>>
>>> From: Ye Li <ye.li@nxp.com>
>>>
>>> Users reported LPDDR4 MR12 value is set to 0 during PHY training,
>>> not the value from FSP timing structure, which cause compliance test 
>>> failed.
>>> The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
>>> but not set in 1D.  According to PHY training application node,
>>> to enable the feature both 1D and 2D need set this field to 1,
>>> otherwise the training result will be incorrect.
>>> The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
>>> MR12 value from message block (FSP structure). So update the LPDDR4
>>> scripts of all mscale to clear CATrainOpt[0].
>>
>> Peng,
>>
>> Is this issue being addressed by an update of the NXP i.MX 8M Family
>> DDR Tools app that generates this code? Is there a reference to this
>> issue online anywhere?
>>
>> A bit unrelated but I would love to see NXP step up and replace the
>> silly NXP i.MX 8M Family DDR Tools windows app with code that could be
>> enabled in the SPL to do the same thing. Personally it's a bit of a
>> joke to require having a Windows PC around to bring up an ARM
>> processor board and I would hope there are folks at NXP that are
>> utterly ashamed at this as well. One could easily use the opensource
>> imx-usb-loader to load an SPL that performed this calibration and
>> training code.
> 
> You find a lot of friends here....most of us will frankly be glad if 
> there will be such as tool, or at least if some code is published to 
> help to port to Linux. NXP story did not show a big interest in the past 
> with the Windows-based MFGTools, but I hoped this was changed with 
> "uuu". Such as tool will really help to improve i.MX support and enlarge 
> NXP community (just a couple of notes: I do not expect Peng can decide 
> this, but he can report our thought internally to NXP).

I have forwarded Tim's to NXP internal. And will also add yours' 
comments about this DDR tool.

I am not the DDR guy, it is out of my power to do the convert, but I'll
try to sell your ideas.

Thanks,
Peng.

> 
> Best regards,
> Stefano
>
diff mbox series

Patch

diff --git a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
index 5faa0021a7..aa23c35094 100644
--- a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
+++ b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
@@ -799,7 +799,6 @@  struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54008, 0x61 },
 	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400d, 0x100 },
 	{ 0x5400f, 0x100 },
 	{ 0x54010, 0x1f7f },
 	{ 0x54012, 0x310 },
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index 9d069fc27a..8c5306d5d2 100755
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -1298,7 +1298,6 @@  struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54008, 0x61 },
 	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400d, 0x100 },
 	{ 0x5400f, 0x100 },
 	{ 0x54010, 0x1f7f },
 	{ 0x54012, 0x310 },
@@ -1330,7 +1329,6 @@  struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54008, 0x61 },
 	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400d, 0x100 },
 	{ 0x5400f, 0x100 },
 	{ 0x54010, 0x1f7f },
 	{ 0x54012, 0x310 },