diff mbox series

[U-Boot,v2,03/13] armv8: mmu: Fix signed shift overflow

Message ID 20180826231332.2491-4-erosca@de.adit-jv.com
State Superseded
Delegated to: Tom Rini
Headers show
Series Import Undefined Behavior Sanitizer | expand

Commit Message

Eugeniu Rosca Aug. 26, 2018, 11:13 p.m. UTC 
Fix the following UBSAN warnings:

------8<-----
CPU: Renesas Electronics R8A7795 rev 2.0
Model: Renesas Salvator-X board based on r8a7795 ES2.0+
 ====================================================================
 UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:72:9
 left shift of 1 by 31 places cannot be represented in type 'int'
 ====================================================================
 ====================================================================
 UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:74:9
 left shift of 1 by 31 places cannot be represented in type 'int'
 ====================================================================
------8<-----

Use (1UL << i) instead of BIT() macro for consistency.

Fixes: ad3d6e88a1a4 ("armv8/mmu: Set bits marked RES1 in TCR")
Fixes: 9bb367a590fe ("arm64: Disable TTBR1 maps in EL1")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
---

Changes in v2:
 - Shorten the summary line
 - Use (1UL << i) instead of BIT() macro for consistency
---
 arch/arm/include/asm/armv8/mmu.h | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

Comments

Tom Rini Aug. 27, 2018, 2:13 p.m. UTC | #1 
On Mon, Aug 27, 2018 at 01:13:21AM +0200, Eugeniu Rosca wrote:

> Fix the following UBSAN warnings:
> 

Reviewed-by: Tom Rini <trini@konsulko.com>
diff mbox series

Patch

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 62d00d15c26d..632d3a442df8 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -78,27 +78,27 @@ 
  * TCR flags.
  */
 #define TCR_T0SZ(x)		((64 - (x)) << 0)
-#define TCR_IRGN_NC		(0 << 8)
-#define TCR_IRGN_WBWA		(1 << 8)
-#define TCR_IRGN_WT		(2 << 8)
-#define TCR_IRGN_WBNWA		(3 << 8)
-#define TCR_IRGN_MASK		(3 << 8)
-#define TCR_ORGN_NC		(0 << 10)
-#define TCR_ORGN_WBWA		(1 << 10)
-#define TCR_ORGN_WT		(2 << 10)
-#define TCR_ORGN_WBNWA		(3 << 10)
-#define TCR_ORGN_MASK		(3 << 10)
-#define TCR_SHARED_NON		(0 << 12)
-#define TCR_SHARED_OUTER	(2 << 12)
-#define TCR_SHARED_INNER	(3 << 12)
-#define TCR_TG0_4K		(0 << 14)
-#define TCR_TG0_64K		(1 << 14)
-#define TCR_TG0_16K		(2 << 14)
-#define TCR_EPD1_DISABLE	(1 << 23)
-
-#define TCR_EL1_RSVD		(1 << 31)
-#define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
-#define TCR_EL3_RSVD		(1 << 31 | 1 << 23)
+#define TCR_IRGN_NC		(0UL << 8)
+#define TCR_IRGN_WBWA		(1UL << 8)
+#define TCR_IRGN_WT		(2UL << 8)
+#define TCR_IRGN_WBNWA		(3UL << 8)
+#define TCR_IRGN_MASK		(3UL << 8)
+#define TCR_ORGN_NC		(0UL << 10)
+#define TCR_ORGN_WBWA		(1UL << 10)
+#define TCR_ORGN_WT		(2UL << 10)
+#define TCR_ORGN_WBNWA		(3UL << 10)
+#define TCR_ORGN_MASK		(3UL << 10)
+#define TCR_SHARED_NON		(0UL << 12)
+#define TCR_SHARED_OUTER	(2UL << 12)
+#define TCR_SHARED_INNER	(3UL << 12)
+#define TCR_TG0_4K		(0UL << 14)
+#define TCR_TG0_64K		(1UL << 14)
+#define TCR_TG0_16K		(2UL << 14)
+#define TCR_EPD1_DISABLE	(1UL << 23)
+
+#define TCR_EL1_RSVD		(1UL << 31)
+#define TCR_EL2_RSVD		(1UL << 31 | 1UL << 23)
+#define TCR_EL3_RSVD		(1UL << 31 | 1UL << 23)
 
 #ifndef __ASSEMBLY__
 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)