| Message ID | 1553189045-4681-5-git-send-email-ley.foon.tan@intel.com |
|---|---|
| State | Accepted |
| Commit | 62e6278d1e7e6628a9ea8b4429a99247fc6a6be6 |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Update Stratix 10 SDRAM driver | expand |
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index 6e8ddcd9f4..c59b77d829 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -36,7 +36,9 @@ memory { device_type = "memory"; - reg = <0 0 0 0x80000000>; /* 2GB */ + /* 4GB */ + reg = <0 0x00000000 0 0x80000000>, + <1 0x80000000 0 0x80000000>; u-boot,dm-pre-reloc; }; };
The stratix10 socdk ships with 4GB of memory. Modify the device tree to represent this. Note that to access 4GB of memory in Stratix 10, due to the IO space from 2GB to 4GB, we use the fact that the DDR controller ignores upper address bits outside of the configured DRAM's size. This means that , the 4GB DRAM is mapped to memory every 4GB. For an 8GB memory, you can either live with the 2GB IO space, and loose access to that memory from the processor, or use the same trick: Loose 2GB of memory: memory { device_type = "memory"; /* 8GB */ /* first 2GB */ reg = <0 0x00000000 0 0x80000000>, /* last 4GB */ <1 0x00000000 1 0x00000000>; u-boot,dm-pre-reloc; }; or to map it all: memory { device_type = "memory"; /* 8GB */ /* first 2GB */ reg = <0 0x00000000 0 0x80000000>, /* next 6GB */ <2 0x80000000 1 0x80000000>; u-boot,dm-pre-reloc; }; Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> --- arch/arm/dts/socfpga_stratix10_socdk.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)