Message ID | 1553189045-4681-1-git-send-email-ley.foon.tan@intel.com |
---|---|
Headers | show |
Series | Update Stratix 10 SDRAM driver | expand |
On 3/21/19 6:23 PM, Ley Foon Tan wrote: > This patchset update Stratix 10 SDRAM driver to support: > - Multi-banks memory > - Stratix 10 support up to 2 memory banks: > Bank 0: Address 0, size 2GB > Bank 1: Address 0x100000000, size 124GB > - Add warm reset boot checking function (Patch[5]) > - Add ECC memory scrubbing support (Patch [6]) > - Use cache enabled + "DC ZVA" instruction to clear memory to zeros > > v1 -> v2: > --------- > - Decode memory bank configuration from device tree > - Use asm volatile() and "memory" clobber > > History: > -------- > v1: https://patchwork.ozlabs.org/cover/1055134/ > > Ley Foon Tan (6): > ddr: altera: stratix10: Move SDRAM size check to SDRAM driver > ddr: altera: Stratix10: Add multi-banks DRAM size check > configs: stratix10: Change CONFIG_NR_DRAM_BANKS to 2 > arm: dts: Stratix10: Modify stratix10 socdk memory node > arm: socfpga: stratix10: Add cpu_has_been_warmreset() > ddr: altera: Stratix10: Add ECC memory scrubbing > > arch/arm/dts/socfpga_stratix10_socdk.dts | 4 +- > .../include/mach/reset_manager_s10.h | 3 + > .../arm/mach-socfpga/include/mach/sdram_s10.h | 9 ++ > arch/arm/mach-socfpga/reset_manager_s10.c | 9 ++ > arch/arm/mach-socfpga/spl_s10.c | 11 -- > configs/socfpga_stratix10_defconfig | 2 +- > drivers/ddr/altera/sdram_s10.c | 136 +++++++++++++++++- > 7 files changed, 159 insertions(+), 15 deletions(-) > Applied all to socfpga/next, thanks