diff mbox series

[U-Boot,v3,1/6] mach-omap2: add AM335x Display PLL register definition

Message ID 1515520896-18833-2-git-send-email-oe5hpm@oevsv.at
State Accepted
Delegated to: Anatolij Gustschin
Headers show
Series am335x-fb: support display PLL for lcd-clock / pixel-clock | expand

Commit Message

Hannes Schmelzer Jan. 9, 2018, 6:01 p.m. UTC 
Adds the register definition of the Display DPLL

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>

---

Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/arch-am33xx/clock.h  | 1 +
 arch/arm/mach-omap2/am33xx/clock_am33xx.c | 7 +++++++
 2 files changed, 8 insertions(+)

Comments

Anatolij Gustschin Jan. 10, 2018, 1:04 p.m. UTC | #1 
On Tue,  9 Jan 2018 19:01:31 +0100
Hannes Schmelzer oe5hpm@oevsv.at wrote:

> Adds the register definition of the Display DPLL
> 
> Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>

Reviewed-by: Anatolij Gustschin <agust@denx.de>
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 5399bb8..9dbcd3a 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -104,6 +104,7 @@  extern const struct dpll_regs dpll_mpu_regs;
 extern const struct dpll_regs dpll_core_regs;
 extern const struct dpll_regs dpll_per_regs;
 extern const struct dpll_regs dpll_ddr_regs;
+extern const struct dpll_regs dpll_disp_regs;
 extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
 extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
 extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
index 1780bbd..9ab4d25 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
@@ -52,6 +52,13 @@  const struct dpll_regs dpll_ddr_regs = {
 	.cm_div_m2_dpll		= CM_WKUP + 0xA0,
 };
 
+const struct dpll_regs dpll_disp_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x98,
+	.cm_idlest_dpll		= CM_WKUP + 0x48,
+	.cm_clksel_dpll		= CM_WKUP + 0x54,
+	.cm_div_m2_dpll		= CM_WKUP + 0xA4,
+};
+
 struct dpll_params dpll_mpu_opp100 = {
 		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_core_opp100 = {