| Message ID | 1433349459-32093-1-git-send-email-andrew@bradfordembedded.com |
|---|---|
| State | Accepted |
| Delegated to: | Simon Glass |
| Headers | show |
On Thu, Jun 4, 2015 at 12:37 AM, <andrew@bradfordembedded.com> wrote: > From: Andrew Bradford <andrew.bradford@kodakalaris.com> > > Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF > and additional SDRAM is mapped from 0x100000000 and up. There is a > physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses. > Because of this, PCI region 3 should only try to use up to the amount of > SDRAM or 0x80000000, which ever is less. > > Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> > --- > v3: Fix build breakage due to semicolon > v2: limit maximum size to lesser of SDRAM or 0x80000000 > --- > arch/x86/cpu/baytrail/pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c > index 6c291f9..48409de 100644 > --- a/arch/x86/cpu/baytrail/pci.c > +++ b/arch/x86/cpu/baytrail/pci.c > @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) > pci_set_region(hose->regions + 3, > 0, > 0, > - gd->ram_size, > + gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, > PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); > > hose->region_count = 4; > -- Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On 3 June 2015 at 18:15, Bin Meng <bmeng.cn@gmail.com> wrote: > On Thu, Jun 4, 2015 at 12:37 AM, <andrew@bradfordembedded.com> wrote: >> From: Andrew Bradford <andrew.bradford@kodakalaris.com> >> >> Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF >> and additional SDRAM is mapped from 0x100000000 and up. There is a >> physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses. >> Because of this, PCI region 3 should only try to use up to the amount of >> SDRAM or 0x80000000, which ever is less. >> >> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> >> --- >> v3: Fix build breakage due to semicolon >> v2: limit maximum size to lesser of SDRAM or 0x80000000 >> --- >> arch/x86/cpu/baytrail/pci.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c >> index 6c291f9..48409de 100644 >> --- a/arch/x86/cpu/baytrail/pci.c >> +++ b/arch/x86/cpu/baytrail/pci.c >> @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) >> pci_set_region(hose->regions + 3, >> 0, >> 0, >> - gd->ram_size, >> + gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, >> PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); >> >> hose->region_count = 4; >> -- > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
On 4 June 2015 at 02:47, Simon Glass <sjg@chromium.org> wrote: > On 3 June 2015 at 18:15, Bin Meng <bmeng.cn@gmail.com> wrote: >> On Thu, Jun 4, 2015 at 12:37 AM, <andrew@bradfordembedded.com> wrote: >>> From: Andrew Bradford <andrew.bradford@kodakalaris.com> >>> >>> Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF >>> and additional SDRAM is mapped from 0x100000000 and up. There is a >>> physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses. >>> Because of this, PCI region 3 should only try to use up to the amount of >>> SDRAM or 0x80000000, which ever is less. >>> >>> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> >>> --- >>> v3: Fix build breakage due to semicolon >>> v2: limit maximum size to lesser of SDRAM or 0x80000000 >>> --- >>> arch/x86/cpu/baytrail/pci.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c >>> index 6c291f9..48409de 100644 >>> --- a/arch/x86/cpu/baytrail/pci.c >>> +++ b/arch/x86/cpu/baytrail/pci.c >>> @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) >>> pci_set_region(hose->regions + 3, >>> 0, >>> 0, >>> - gd->ram_size, >>> + gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, >>> PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); >>> >>> hose->region_count = 4; >>> -- >> >> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > Acked-by: Simon Glass <sjg@chromium.org> Applied to u-boot-x86, thanks!
diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c index 6c291f9..48409de 100644 --- a/arch/x86/cpu/baytrail/pci.c +++ b/arch/x86/cpu/baytrail/pci.c @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) pci_set_region(hose->regions + 3, 0, 0, - gd->ram_size, + gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4;