From patchwork Wed Jun 3 16:37:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bradford X-Patchwork-Id: 480031 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A0AD71401AB for ; Thu, 4 Jun 2015 02:38:50 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=bradfordembedded.com header.i=@bradfordembedded.com header.b=IwDd8v6E; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b=AUSMBhl7; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3BD384B65F; Wed, 3 Jun 2015 18:38:48 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tR_WM9_AfRSi; Wed, 3 Jun 2015 18:38:47 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9EBA24B657; Wed, 3 Jun 2015 18:38:47 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 86A304B657 for ; Wed, 3 Jun 2015 18:38:45 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lEZ9uS0fy2x8 for ; Wed, 3 Jun 2015 18:38:45 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by theia.denx.de (Postfix) with ESMTPS id 425AA4B656 for ; Wed, 3 Jun 2015 18:38:42 +0200 (CEST) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 22C1020B7E; Wed, 3 Jun 2015 12:38:40 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 03 Jun 2015 12:38:40 -0400 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d= bradfordembedded.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=CnSiA bnFA17uC8xIEFjAuNj5G1k=; b=IwDd8v6E6G/1qaee6+VQOj29mIWgWJb/pyEBy tXp+wXEOU0h4G9nAD7jQ4J+EsfjFf8vqTHc0LOCeDIn79tIZ13mLOnMOnpmmCANF oQFelsMlLdGHB3DBrBn29G7SzLxYi/3FxwtSu39urG6YQzf42QJn1zpJJp/4AiXH p41pAQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-sasl-enc:x-sasl-enc; s=smtpout; bh=CnSi AbnFA17uC8xIEFjAuNj5G1k=; b=AUSMBhl7SxJ681/KnNlG8gg4wXBWXY/TUyr2 xm+u5OVhnxYoDBeXd0TVIEvHINXxGQPaR57OhHFtVP7PKK8dkZUDu+ZweEJ1midZ LO1Bvdcz1p62eVBn2Cq7QOIVR+v0NCsuIxbUZy0OJeQ2BY60T40xYtixTumjRJ74 t5+u5h4= X-Sasl-enc: wZ61Cw6r99war8GDW3ltPgT1H8sP4khxXXny9km2mRBF 1433349519 Received: from rhino.kodakalaris.net (unknown [198.140.222.129]) by mail.messagingengine.com (Postfix) with ESMTPA id C3A916801F3; Wed, 3 Jun 2015 12:38:39 -0400 (EDT) From: andrew@bradfordembedded.com To: u-boot@lists.denx.de, Simon Glass , Graeme Russ , bmeng.cn@gmail.com Date: Wed, 3 Jun 2015 12:37:39 -0400 Message-Id: <1433349459-32093-1-git-send-email-andrew@bradfordembedded.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432321778-23960-1-git-send-email-andrew@bradfordembedded.com> References: <1432321778-23960-1-git-send-email-andrew@bradfordembedded.com> Cc: Andrew Bradford Subject: [U-Boot] [PATCH v3] x86: baytrail: pci region 3 is not always mapped to end of ram X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Andrew Bradford Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF and additional SDRAM is mapped from 0x100000000 and up. There is a physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses. Because of this, PCI region 3 should only try to use up to the amount of SDRAM or 0x80000000, which ever is less. Signed-off-by: Andrew Bradford Reviewed-by: Bin Meng Acked-by: Simon Glass --- v3: Fix build breakage due to semicolon v2: limit maximum size to lesser of SDRAM or 0x80000000 --- arch/x86/cpu/baytrail/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c index 6c291f9..48409de 100644 --- a/arch/x86/cpu/baytrail/pci.c +++ b/arch/x86/cpu/baytrail/pci.c @@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose) pci_set_region(hose->regions + 3, 0, 0, - gd->ram_size, + gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4;