| Message ID | 20230530133327.178278-1-francesco@dolcini.it |
|---|---|
| Headers | show |
| Series | common/memsize.c: Fix get_ram_size() when cache is enabled | expand |
On Tue, 30 May 2023 15:33:25 +0200, Francesco Dolcini wrote: > From: Francesco Dolcini <francesco.dolcini@toradex.com> > > Ensure that every write is flushed to memory and afterward reads are > from memory. > Since the algorithm rely on the fact that accessing to not existent > memory lead to write at addr / 2 without this modification accesses > to aliased (not physically present) addresses are cached and > wrong size is returned. > > [...] Applied to u-boot/next, thanks!
From: Francesco Dolcini <francesco.dolcini@toradex.com> Ensure that every write is flushed to memory and afterward reads are from memory. Since the algorithm rely on the fact that accessing to not existent memory lead to write at addr / 2 without this modification accesses to aliased (not physically present) addresses are cached and wrong size is returned. This was discovered while working on a TI AM625 based board where cache is normally enabled, see commit c02712a74849 ("arm: mach-k3: Enable dcache in SPL"). Test results here: https://github.com/u-boot/u-boot/pull/293 v2: * added additional patch to fix sandbox build * ensure that the changes are fine with every arch/build, check if cache is enabled and check for cache line size define Emanuele Ghidoli (2): sandbox: Add a dummy dcache_status() function common/memsize.c: Fix get_ram_size() when cache is enabled arch/sandbox/cpu/cpu.c | 5 +++++ common/memsize.c | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+)