From patchwork Tue May 30 13:33:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francesco Dolcini X-Patchwork-Id: 1787583 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QVtf93pv8z20Pc for ; Tue, 30 May 2023 23:34:09 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0980985AFF; Tue, 30 May 2023 15:33:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=dolcini.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 396D785AFF; Tue, 30 May 2023 15:33:42 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail11.truemail.it (mail11.truemail.it [IPv6:2001:4b7e:0:8::81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6757B85F01 for ; Tue, 30 May 2023 15:33:33 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=dolcini.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=francesco@dolcini.it Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id B6104209A7; Tue, 30 May 2023 15:33:32 +0200 (CEST) From: Francesco Dolcini To: u-boot@lists.denx.de, Tom Rini , Simon Glass Cc: Emanuele Ghidoli , Francesco Dolcini Subject: [PATCH v2 1/2] sandbox: Add a dummy dcache_status() function Date: Tue, 30 May 2023 15:33:26 +0200 Message-Id: <20230530133327.178278-2-francesco@dolcini.it> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230530133327.178278-1-francesco@dolcini.it> References: <20230530133327.178278-1-francesco@dolcini.it> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Emanuele Ghidoli This adds dcache_status() so that code using it can build without error on sandbox. This is required in preparation of adding cache handling into get_ram_size function. Signed-off-by: Emanuele Ghidoli Signed-off-by: Francesco Dolcini Reviewed-by: Simon Glass --- arch/sandbox/cpu/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 51496338ad60..a1c5c7c4311a 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -286,6 +286,11 @@ void sandbox_set_enable_pci_map(int enable) enable_pci_map = enable; } +int dcache_status(void) +{ + return 1; +} + void flush_dcache_range(unsigned long start, unsigned long stop) { } From patchwork Tue May 30 13:33:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francesco Dolcini X-Patchwork-Id: 1787584 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QVtfL0RSdz20Pc for ; Tue, 30 May 2023 23:34:18 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 336BD85F52; Tue, 30 May 2023 15:33:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=dolcini.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id EB07885ED2; Tue, 30 May 2023 15:33:42 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3C2CE85EE5 for ; Tue, 30 May 2023 15:33:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=dolcini.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=francesco@dolcini.it Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id 115B520B0C; Tue, 30 May 2023 15:33:33 +0200 (CEST) From: Francesco Dolcini To: =?utf-8?q?Pali_Roh=C3=A1r?= , u-boot@lists.denx.de, Tom Rini , Simon Glass Cc: Emanuele Ghidoli , Francesco Dolcini Subject: [PATCH v2 2/2] common/memsize.c: Fix get_ram_size() when cache is enabled Date: Tue, 30 May 2023 15:33:27 +0200 Message-Id: <20230530133327.178278-3-francesco@dolcini.it> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230530133327.178278-1-francesco@dolcini.it> References: <20230530133327.178278-1-francesco@dolcini.it> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Emanuele Ghidoli Ensure that every write is flushed to memory and afterward reads are from memory. Since the algorithm rely on the fact that accessing to not existent memory lead to write at addr / 2 without this modification accesses to aliased (not physically present) addresses are cached and wrong size is returned. This was discovered while working on a TI AM625 based board where cache is normally enabled, see commit c02712a74849 ("arm: mach-k3: Enable dcache in SPL"). Signed-off-by: Emanuele Ghidoli Signed-off-by: Francesco Dolcini --- v2: * check if CONFIG_SYS_CACHELINE_SIZE is defined * do flush only when cache is enabled --- common/memsize.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/common/memsize.c b/common/memsize.c index 66d5be6a1ff3..d646df8b04cb 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -7,9 +7,18 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_CACHELINE_SIZE +# define MEMSIZE_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE +#else +/* Just use the greatest cache flush alignment requirement I'm aware of */ +# define MEMSIZE_CACHELINE_SIZE 128 +#endif + #ifdef __PPC__ /* * At least on G2 PowerPC cores, sequential accesses to non-existent @@ -20,6 +29,15 @@ DECLARE_GLOBAL_DATA_PTR; # define sync() /* nothing */ #endif +static void dcache_flush_invalidate(volatile long *p) +{ + uintptr_t start, stop; + start = ALIGN_DOWN((uintptr_t)p, MEMSIZE_CACHELINE_SIZE); + stop = start + MEMSIZE_CACHELINE_SIZE; + flush_dcache_range(start, stop); + invalidate_dcache_range(start, stop); +} + /* * Check memory range for valid RAM. A simple memory test determines * the actually available RAM size between addresses `base' and @@ -34,6 +52,7 @@ long get_ram_size(long *base, long maxsize) long val; long size; int i = 0; + int dcache_en = dcache_status(); for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ @@ -41,6 +60,8 @@ long get_ram_size(long *base, long maxsize) save[i++] = *addr; sync(); *addr = ~cnt; + if (dcache_en) + dcache_flush_invalidate(addr); } addr = base; @@ -50,6 +71,9 @@ long get_ram_size(long *base, long maxsize) *addr = 0; sync(); + if (dcache_en) + dcache_flush_invalidate(addr); + if ((val = *addr) != 0) { /* Restore the original data before leaving the function. */ sync();