[v2,00/16] riscv: k210: Enable use of AI ram bank

This ram bank was previously unusable because PLL1 was not started correctly.
This series fixes that bug, and allows U-Boot to relocate into the AI ram. This
provides an extra 2M of space in which to load payloads.

Second time around and I realized that the bypass clock is no longer necessary
(yay). This also necessitates a few more small fixups. I've also added some
minor patches to bring the device tree and clock driver closer to what Linux has
(or will have). This should be the last round of additions to this series.

Changes in v2:
- Don't re-enable the PLL
- Remove bypass clock, which is no longer necessary
- Simplify PLL instantiation
- Modify clock tree so clint is a child of aclk
- Sync memory dts node with Linux
- Use correct aisram clock

Sean Anderson (16):
  clk: k210: Fix PLLs not being enabled
  clk: k210: Fix PLL enable always getting taken
  clk: k210: Remove bypass clock
  clk: k210: Remove k210_register_pll
  clk: k210: Move the clint clock to under aclk
  clk: Add support for the k210 clock driver pre-relocation
  riscv: Enable some devices pre-relocation
  lib: fdt: Add fdtdec_setup_mem_size_base_highest
  test: Add a test for fdtdec_setup_mem_size_base et al.
  ram: Add driver for K210 SRAM
  ram: sifive: Default to y only if compiling for fu540
  riscv: Probe ram in dram_init
  riscv: Enable AI ram on K210
  riscv: k210: Rename airam to aisram
  riscv: k210: Use AI as the parent clock of aisram, not PLL1
  riscv: Don't reserve AI ram in k210 dts

 MAINTAINERS                        |   1 +
 arch/riscv/cpu/generic/dram.c      |  26 +++
 arch/riscv/dts/k210.dtsi           |  22 +--
 arch/sandbox/dts/test.dts          |  12 ++
 board/sipeed/maix/Kconfig          |   2 +
 board/sipeed/maix/maix.c           |  26 ---
 configs/sandbox64_defconfig        |   2 +-
 configs/sandbox_defconfig          |   2 +-
 configs/sandbox_flattree_defconfig |   2 +-
 configs/sipeed_maix_bitm_defconfig |   1 +
 drivers/clk/kendryte/Makefile      |   2 +-
 drivers/clk/kendryte/bypass.c      | 273 -----------------------------
 drivers/clk/kendryte/clk.c         |  61 +++----
 drivers/clk/kendryte/pll.c         |  26 +--
 drivers/ram/Kconfig                |   7 +
 drivers/ram/Makefile               |   1 +
 drivers/ram/kendryte.c             |  56 ++++++
 drivers/ram/sifive/Kconfig         |   2 +-
 include/configs/sipeed-maix.h      |   4 -
 include/fdtdec.h                   |  19 +-
 include/kendryte/bypass.h          |  31 ----
 include/kendryte/pll.h             |   4 -
 lib/fdtdec.c                       |  34 +++-
 test/dm/fdtdec.c                   |  38 ++++
 24 files changed, 230 insertions(+), 424 deletions(-)
 delete mode 100644 drivers/clk/kendryte/bypass.c
 create mode 100644 drivers/ram/kendryte.c
 delete mode 100644 include/kendryte/bypass.h

On 10/12/20 2:13 PM, Sean Anderson wrote:
> This ram bank was previously unusable because PLL1 was not started correctly.
> This series fixes that bug, and allows U-Boot to relocate into the AI ram. This
> provides an extra 2M of space in which to load payloads.
> 
> Second time around and I realized that the bypass clock is no longer necessary
> (yay). This also necessitates a few more small fixups. I've also added some
> minor patches to bring the device tree and clock driver closer to what Linux has
> (or will have). This should be the last round of additions to this series.

I discovered that the clock changes I made cause problems with
non-default PLL frequencies (specifically the removal of the bypass
clock). I've been working on-and-off on a v3 to fix these problems.

--Sean

> Changes in v2:
> - Don't re-enable the PLL
> - Remove bypass clock, which is no longer necessary
> - Simplify PLL instantiation
> - Modify clock tree so clint is a child of aclk
> - Sync memory dts node with Linux
> - Use correct aisram clock
> 
> Sean Anderson (16):
>   clk: k210: Fix PLLs not being enabled
>   clk: k210: Fix PLL enable always getting taken
>   clk: k210: Remove bypass clock
>   clk: k210: Remove k210_register_pll
>   clk: k210: Move the clint clock to under aclk
>   clk: Add support for the k210 clock driver pre-relocation
>   riscv: Enable some devices pre-relocation
>   lib: fdt: Add fdtdec_setup_mem_size_base_highest
>   test: Add a test for fdtdec_setup_mem_size_base et al.
>   ram: Add driver for K210 SRAM
>   ram: sifive: Default to y only if compiling for fu540
>   riscv: Probe ram in dram_init
>   riscv: Enable AI ram on K210
>   riscv: k210: Rename airam to aisram
>   riscv: k210: Use AI as the parent clock of aisram, not PLL1
>   riscv: Don't reserve AI ram in k210 dts
> 
>  MAINTAINERS                        |   1 +
>  arch/riscv/cpu/generic/dram.c      |  26 +++
>  arch/riscv/dts/k210.dtsi           |  22 +--
>  arch/sandbox/dts/test.dts          |  12 ++
>  board/sipeed/maix/Kconfig          |   2 +
>  board/sipeed/maix/maix.c           |  26 ---
>  configs/sandbox64_defconfig        |   2 +-
>  configs/sandbox_defconfig          |   2 +-
>  configs/sandbox_flattree_defconfig |   2 +-
>  configs/sipeed_maix_bitm_defconfig |   1 +
>  drivers/clk/kendryte/Makefile      |   2 +-
>  drivers/clk/kendryte/bypass.c      | 273 -----------------------------
>  drivers/clk/kendryte/clk.c         |  61 +++----
>  drivers/clk/kendryte/pll.c         |  26 +--
>  drivers/ram/Kconfig                |   7 +
>  drivers/ram/Makefile               |   1 +
>  drivers/ram/kendryte.c             |  56 ++++++
>  drivers/ram/sifive/Kconfig         |   2 +-
>  include/configs/sipeed-maix.h      |   4 -
>  include/fdtdec.h                   |  19 +-
>  include/kendryte/bypass.h          |  31 ----
>  include/kendryte/pll.h             |   4 -
>  lib/fdtdec.c                       |  34 +++-
>  test/dm/fdtdec.c                   |  38 ++++
>  24 files changed, 230 insertions(+), 424 deletions(-)
>  delete mode 100644 drivers/clk/kendryte/bypass.c
>  create mode 100644 drivers/ram/kendryte.c
>  delete mode 100644 include/kendryte/bypass.h
>