| Message ID | 1559207024-22181-1-git-send-email-ley.foon.tan@intel.com |
|---|---|
| Headers | show |
| Series | Add Intel Agilex SoC support | expand |
On Thu, May 30, 2019 at 5:03 PM Ley Foon Tan <ley.foon.tan@intel.com> wrote: > > This is 2nd version of patchset to add Intel Agilex SoC[1] support. > This patchset needs to apply after patch in [2] for Designware i2c clock from DM. > > Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore > hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM, > other IPs have minor changes compared to Stratix 10. > > Intel Agilex HPS TRM: > https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/mnl-1100.pdf > > v1->v2: > ------- > - Change clock driver to DM > - Reuse base_addr_s10.h from S10 > - Add system_manager_s10_agilex_common.h > - Update commit message for CCU patch > - Update Linux commit id in dts/dtsi patch Any comment on this v2 patch series? Thanks. Regards Ley Foon
On 6/10/19 8:31 AM, Ley Foon Tan wrote: > On Thu, May 30, 2019 at 5:03 PM Ley Foon Tan <ley.foon.tan@intel.com> wrote: >> >> This is 2nd version of patchset to add Intel Agilex SoC[1] support. >> This patchset needs to apply after patch in [2] for Designware i2c clock from DM. >> >> Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore >> hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM, >> other IPs have minor changes compared to Stratix 10. >> >> Intel Agilex HPS TRM: >> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/mnl-1100.pdf >> >> v1->v2: >> ------- >> - Change clock driver to DM >> - Reuse base_addr_s10.h from S10 >> - Add system_manager_s10_agilex_common.h >> - Update commit message for CCU patch >> - Update Linux commit id in dts/dtsi patch > > Any comment on this v2 patch series? I'd like to see a review from Dinh or Simon.
Marek Vasut <marex@denx.de> schrieb am Di., 11. Juni 2019, 16:01: > On 6/10/19 8:31 AM, Ley Foon Tan wrote: > > On Thu, May 30, 2019 at 5:03 PM Ley Foon Tan <ley.foon.tan@intel.com> > wrote: > >> > >> This is 2nd version of patchset to add Intel Agilex SoC[1] support. > >> This patchset needs to apply after patch in [2] for Designware i2c > clock from DM. > >> > >> Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore > >> hard processor system (HPS). New IPs in Agilex are CCU, clock manager > and SDRAM, > >> other IPs have minor changes compared to Stratix 10. > >> > >> Intel Agilex HPS TRM: > >> > https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/mnl-1100.pdf > >> > >> v1->v2: > >> ------- > >> - Change clock driver to DM > >> - Reuse base_addr_s10.h from S10 > >> - Add system_manager_s10_agilex_common.h > >> - Update commit message for CCU patch > >> - Update Linux commit id in dts/dtsi patch > > > > Any comment on this v2 patch series? > > I'd like to see a review from Dinh or Simon. > That's on my list. Sorry, but I'm really really short on time for U-Boot, lately :-( I'll see what I can do to review it soon. Regards, Simon >
Am 30.05.2019 um 11:03 schrieb Ley Foon Tan: > This is 2nd version of patchset to add Intel Agilex SoC[1] support. If this is v2, why doesn't the subject say so? > This patchset needs to apply after patch in [2] for Designware i2c clock from DM. > > Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore > hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM, > other IPs have minor changes compared to Stratix 10. > > Intel Agilex HPS TRM: > https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/mnl-1100.pdf > > v1->v2: > ------- > - Change clock driver to DM > - Reuse base_addr_s10.h from S10 > - Add system_manager_s10_agilex_common.h > - Update commit message for CCU patch > - Update Linux commit id in dts/dtsi patch > > History: > --------- > [v1]: https://patchwork.ozlabs.org/cover/1097830/ > > [1]: https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.html > [2]: https://patchwork.ozlabs.org/patch/1107608/ This has changed to v2 by now (just for the record): https://patchwork.ozlabs.org/patch/1114251/ Regards, Simon > > Ley Foon Tan (15): > arm: socfpga: agilex: Add base address for Intel Agilex SoC > arm: socfpga: Move firewall code to firewall file > arm: socfpga: Move Stratix10 and Agilex reset manager common code > arm: socfpga: agilex: Add reset manager support > arm: socfpga: Move Stratix10 and Agilex system manager common code > arm: socfpga: agilex: Add system manager support > clk: agilex: Add clock driver for Agilex. > arm: socfpga: agilex: Add clock manager support > arm: socfpga: agilex: Add CCU support for Agilex > ddr: altera: Restructure Stratix 10 SDRAM driver > ddr: altera: agilex: Add SDRAM driver for Agilex > board: intel: agilex: Add socdk board support for Intel Agilex SoC > arm: socfpga: agilex: Add SPL for Agilex SoC > arm: dts: agilex: Add base dtsi and devkit dts > arm: socfpga: agilex: Enable Agilex SoC build > > arch/arm/Kconfig | 4 +- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/socfpga_agilex.dtsi | 495 +++++++++++++++ > arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 71 +++ > arch/arm/dts/socfpga_agilex_socdk.dts | 136 +++++ > arch/arm/mach-socfpga/Kconfig | 15 + > arch/arm/mach-socfpga/Makefile | 18 + > arch/arm/mach-socfpga/ccu_agilex.c | 99 +++ > arch/arm/mach-socfpga/clock_manager_agilex.c | 87 +++ > arch/arm/mach-socfpga/firewall.c | 97 +++ > .../mach-socfpga/include/mach/base_addr_s10.h | 4 + > .../mach-socfpga/include/mach/ccu_agilex.h | 67 +++ > .../mach-socfpga/include/mach/clock_manager.h | 2 + > .../include/mach/clock_manager_agilex.h | 329 ++++++++++ > .../mach/{firewall_s10.h => firewall.h} | 10 +- > .../mach-socfpga/include/mach/reset_manager.h | 29 + > .../include/mach/reset_manager_agilex.h | 38 ++ > .../include/mach/reset_manager_s10.h | 79 --- > .../include/mach/system_manager.h | 2 + > ..._manager_s10.h => system_manager_agilex.h} | 89 +-- > .../include/mach/system_manager_s10.h | 46 +- > .../mach/system_manager_s10_agilex_common.h | 60 ++ > arch/arm/mach-socfpga/reset_manager.c | 9 +- > arch/arm/mach-socfpga/spl_agilex.c | 100 +++ > arch/arm/mach-socfpga/spl_s10.c | 84 +-- > board/intel/agilex-socdk/MAINTAINERS | 7 + > board/intel/agilex-socdk/Makefile | 7 + > board/intel/agilex-socdk/socfpga.c | 7 + > configs/socfpga_agilex_defconfig | 57 ++ > drivers/clk/altera/Makefile | 1 + > drivers/clk/altera/clk-agilex.c | 568 ++++++++++++++++++ > drivers/ddr/altera/Kconfig | 6 +- > drivers/ddr/altera/Makefile | 3 +- > drivers/ddr/altera/sdram_agilex.c | 158 +++++ > drivers/ddr/altera/sdram_common.c | 308 ++++++++++ > .../altera/{sdram_s10.h => sdram_common.h} | 75 +-- > drivers/ddr/altera/sdram_s10.c | 302 +--------- > drivers/ddr/altera/sdram_s10.h | 148 ----- > include/configs/socfpga_agilex_socdk.h | 208 +++++++ > include/dt-bindings/clock/stratix10-clock.h | 84 +++ > 40 files changed, 3140 insertions(+), 770 deletions(-) > create mode 100644 arch/arm/dts/socfpga_agilex.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts > create mode 100644 arch/arm/mach-socfpga/ccu_agilex.c > create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c > create mode 100644 arch/arm/mach-socfpga/firewall.c > create mode 100644 arch/arm/mach-socfpga/include/mach/ccu_agilex.h > create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h > rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%) > create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h > copy arch/arm/mach-socfpga/include/mach/{system_manager_s10.h => system_manager_agilex.h} (51%) > create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10_agilex_common.h > create mode 100644 arch/arm/mach-socfpga/spl_agilex.c > create mode 100644 board/intel/agilex-socdk/MAINTAINERS > create mode 100644 board/intel/agilex-socdk/Makefile > create mode 100644 board/intel/agilex-socdk/socfpga.c > create mode 100644 configs/socfpga_agilex_defconfig > create mode 100644 drivers/clk/altera/clk-agilex.c > create mode 100644 drivers/ddr/altera/sdram_agilex.c > create mode 100644 drivers/ddr/altera/sdram_common.c > copy drivers/ddr/altera/{sdram_s10.h => sdram_common.h} (78%) > create mode 100644 include/configs/socfpga_agilex_socdk.h > create mode 100644 include/dt-bindings/clock/stratix10-clock.h >
On Tue, Jun 25, 2019 at 3:53 AM Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> wrote: > > Am 30.05.2019 um 11:03 schrieb Ley Foon Tan: > > This is 2nd version of patchset to add Intel Agilex SoC[1] support. > > If this is v2, why doesn't the subject say so? This is v2. Forgot change the subject to v2 after sent the patches. Sorry about that. Regards Ley Foon
This is 2nd version of patchset to add Intel Agilex SoC[1] support. This patchset needs to apply after patch in [2] for Designware i2c clock from DM. Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM, other IPs have minor changes compared to Stratix 10. Intel Agilex HPS TRM: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/mnl-1100.pdf v1->v2: ------- - Change clock driver to DM - Reuse base_addr_s10.h from S10 - Add system_manager_s10_agilex_common.h - Update commit message for CCU patch - Update Linux commit id in dts/dtsi patch History: --------- [v1]: https://patchwork.ozlabs.org/cover/1097830/ [1]: https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.html [2]: https://patchwork.ozlabs.org/patch/1107608/ Ley Foon Tan (15): arm: socfpga: agilex: Add base address for Intel Agilex SoC arm: socfpga: Move firewall code to firewall file arm: socfpga: Move Stratix10 and Agilex reset manager common code arm: socfpga: agilex: Add reset manager support arm: socfpga: Move Stratix10 and Agilex system manager common code arm: socfpga: agilex: Add system manager support clk: agilex: Add clock driver for Agilex. arm: socfpga: agilex: Add clock manager support arm: socfpga: agilex: Add CCU support for Agilex ddr: altera: Restructure Stratix 10 SDRAM driver ddr: altera: agilex: Add SDRAM driver for Agilex board: intel: agilex: Add socdk board support for Intel Agilex SoC arm: socfpga: agilex: Add SPL for Agilex SoC arm: dts: agilex: Add base dtsi and devkit dts arm: socfpga: agilex: Enable Agilex SoC build arch/arm/Kconfig | 4 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex.dtsi | 495 +++++++++++++++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 71 +++ arch/arm/dts/socfpga_agilex_socdk.dts | 136 +++++ arch/arm/mach-socfpga/Kconfig | 15 + arch/arm/mach-socfpga/Makefile | 18 + arch/arm/mach-socfpga/ccu_agilex.c | 99 +++ arch/arm/mach-socfpga/clock_manager_agilex.c | 87 +++ arch/arm/mach-socfpga/firewall.c | 97 +++ .../mach-socfpga/include/mach/base_addr_s10.h | 4 + .../mach-socfpga/include/mach/ccu_agilex.h | 67 +++ .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_agilex.h | 329 ++++++++++ .../mach/{firewall_s10.h => firewall.h} | 10 +- .../mach-socfpga/include/mach/reset_manager.h | 29 + .../include/mach/reset_manager_agilex.h | 38 ++ .../include/mach/reset_manager_s10.h | 79 --- .../include/mach/system_manager.h | 2 + ..._manager_s10.h => system_manager_agilex.h} | 89 +-- .../include/mach/system_manager_s10.h | 46 +- .../mach/system_manager_s10_agilex_common.h | 60 ++ arch/arm/mach-socfpga/reset_manager.c | 9 +- arch/arm/mach-socfpga/spl_agilex.c | 100 +++ arch/arm/mach-socfpga/spl_s10.c | 84 +-- board/intel/agilex-socdk/MAINTAINERS | 7 + board/intel/agilex-socdk/Makefile | 7 + board/intel/agilex-socdk/socfpga.c | 7 + configs/socfpga_agilex_defconfig | 57 ++ drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex.c | 568 ++++++++++++++++++ drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_agilex.c | 158 +++++ drivers/ddr/altera/sdram_common.c | 308 ++++++++++ .../altera/{sdram_s10.h => sdram_common.h} | 75 +-- drivers/ddr/altera/sdram_s10.c | 302 +--------- drivers/ddr/altera/sdram_s10.h | 148 ----- include/configs/socfpga_agilex_socdk.h | 208 +++++++ include/dt-bindings/clock/stratix10-clock.h | 84 +++ 40 files changed, 3140 insertions(+), 770 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts create mode 100644 arch/arm/mach-socfpga/ccu_agilex.c create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c create mode 100644 arch/arm/mach-socfpga/firewall.c create mode 100644 arch/arm/mach-socfpga/include/mach/ccu_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h copy arch/arm/mach-socfpga/include/mach/{system_manager_s10.h => system_manager_agilex.h} (51%) create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10_agilex_common.h create mode 100644 arch/arm/mach-socfpga/spl_agilex.c create mode 100644 board/intel/agilex-socdk/MAINTAINERS create mode 100644 board/intel/agilex-socdk/Makefile create mode 100644 board/intel/agilex-socdk/socfpga.c create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 drivers/clk/altera/clk-agilex.c create mode 100644 drivers/ddr/altera/sdram_agilex.c create mode 100644 drivers/ddr/altera/sdram_common.c copy drivers/ddr/altera/{sdram_s10.h => sdram_common.h} (78%) create mode 100644 include/configs/socfpga_agilex_socdk.h create mode 100644 include/dt-bindings/clock/stratix10-clock.h