| Message ID | 1559207024-22181-2-git-send-email-ley.foon.tan@intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Add Intel Agilex SoC support | expand |
Am 30.05.2019 um 11:03 schrieb Ley Foon Tan: > Add base address for Intel Agilex SoC. > > Reuse base_addr_s10.h for Agilex, only one base address is > different from S10. > > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> > --- Wait, this is v2, right? What hss changed since v1? I notice v2 has 15 patches while v1 had 14. Have you ever considered using patman and its helper tags? It would greatly reduce the effort for reviewers to keep things consistent and including a list of changes in each patch. I mean, when reading v2, I want to rely on you saying "patches 1, 3, and 5 of 14 have changed, the rest have not" to speed up my reviewing. Patman really helps you with that, just try it! And if you don't want to, well, look at how other developers send their multi-version patches... Regards, Simon > arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h > index 1f549d7e70..d3eca65e97 100644 > --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h > @@ -10,7 +10,11 @@ > #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 > #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 > #define SOCFPGA_SDR_ADDRESS 0xf8011000 > +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX > +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 > +#else > #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 > +#endif > #define SOCFPGA_SMMU_ADDRESS 0xfa000000 > #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 > #define SOCFPGA_UART0_ADDRESS 0xffc02000 >
On Tue, Jun 25, 2019 at 4:00 AM Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> wrote: > > Am 30.05.2019 um 11:03 schrieb Ley Foon Tan: > > Add base address for Intel Agilex SoC. > > > > Reuse base_addr_s10.h for Agilex, only one base address is > > different from S10. > > > > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> > > --- > > Wait, this is v2, right? What hss changed since v1? I notice v2 has 15 > patches while v1 had 14. > > Have you ever considered using patman and its helper tags? It would > greatly reduce the effort for reviewers to keep things consistent and > including a list of changes in each patch. > > I mean, when reading v2, I want to rely on you saying "patches 1, 3, and > 5 of 14 have changed, the rest have not" to speed up my reviewing. > Patman really helps you with that, just try it! And if you don't want > to, well, look at how other developers send their multi-version patches... > > Regards, > Simon > I will look into Patman for next revision. Here is summary for this series: Patch 1, 5, 6, 7, 8, 13, 14, 15 have changed, the rest have not. *Patch 7 is new patch for clock manager driver with DM. Regards Ley Foon
On 6/24/19 8:16 PM, Ley Foon Tan wrote: > On Tue, Jun 25, 2019 at 4:00 AM Simon Goldschmidt > <simon.k.r.goldschmidt@gmail.com> wrote: >> >> Am 30.05.2019 um 11:03 schrieb Ley Foon Tan: >>> Add base address for Intel Agilex SoC. >>> >>> Reuse base_addr_s10.h for Agilex, only one base address is >>> different from S10. >>> >>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> >>> --- >> >> Wait, this is v2, right? What hss changed since v1? I notice v2 has 15 >> patches while v1 had 14. >> >> Have you ever considered using patman and its helper tags? It would >> greatly reduce the effort for reviewers to keep things consistent and >> including a list of changes in each patch. >> >> I mean, when reading v2, I want to rely on you saying "patches 1, 3, and >> 5 of 14 have changed, the rest have not" to speed up my reviewing. >> Patman really helps you with that, just try it! And if you don't want >> to, well, look at how other developers send their multi-version patches... >> >> Regards, >> Simon >> > I will look into Patman for next revision. > > Here is summary for this series: > > Patch 1, 5, 6, 7, 8, 13, 14, 15 have changed, the rest have not. > *Patch 7 is new patch for clock manager driver with DM. > Can you just resend the series with the version changes properly stated in each patch? Also, its polite to include people in subsequent versions that have made comments in previous version. Dinh
On Tue, Jun 25, 2019 at 10:03 PM Dinh Nguyen <dinguyen@kernel.org> wrote: > > > > On 6/24/19 8:16 PM, Ley Foon Tan wrote: > > On Tue, Jun 25, 2019 at 4:00 AM Simon Goldschmidt > > <simon.k.r.goldschmidt@gmail.com> wrote: > >> > >> Am 30.05.2019 um 11:03 schrieb Ley Foon Tan: > >>> Add base address for Intel Agilex SoC. > >>> > >>> Reuse base_addr_s10.h for Agilex, only one base address is > >>> different from S10. > >>> > >>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> > >>> --- > >> > >> Wait, this is v2, right? What hss changed since v1? I notice v2 has 15 > >> patches while v1 had 14. > >> > >> Have you ever considered using patman and its helper tags? It would > >> greatly reduce the effort for reviewers to keep things consistent and > >> including a list of changes in each patch. > >> > >> I mean, when reading v2, I want to rely on you saying "patches 1, 3, and > >> 5 of 14 have changed, the rest have not" to speed up my reviewing. > >> Patman really helps you with that, just try it! And if you don't want > >> to, well, look at how other developers send their multi-version patches... > >> > >> Regards, > >> Simon > >> > > I will look into Patman for next revision. > > > > Here is summary for this series: > > > > Patch 1, 5, 6, 7, 8, 13, 14, 15 have changed, the rest have not. > > *Patch 7 is new patch for clock manager driver with DM. > > > > Can you just resend the series with the version changes properly stated > in each patch? Also, its polite to include people in subsequent versions > that have made comments in previous version. > Okay, will resend again. Thanks. Regards Ley Foon
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h index 1f549d7e70..d3eca65e97 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -10,7 +10,11 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 +#else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 +#endif #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000
Add base address for Intel Agilex SoC. Reuse base_addr_s10.h for Agilex, only one base address is different from S10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 ++++ 1 file changed, 4 insertions(+)