[04/65] target/riscv: Override some csr ops for XTheadVector

Message ID	20240412073735.76413-5-eric.huang@linux.alibaba.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Huang Tao <eric.huang@linux.alibaba.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, Huang Tao <eric.huang@linux.alibaba.com> Subject: [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector Date: Fri, 12 Apr 2024 15:36:34 +0800 Message-ID: <20240412073735.76413-5-eric.huang@linux.alibaba.com> In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com> References: <20240412073735.76413-1-eric.huang@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=115.124.30.111; envelope-from=eric.huang@linux.alibaba.com; helo=out30-111.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	target/riscv: Support XTheadVector extension \| expand [00/65] target/riscv: Support XTheadVector extension [01/65] riscv: thead: Add th.sxstatus CSR emulation [02/65] target/riscv: Reuse th_csr.c to add user-mode csrs [03/65] target/riscv: Add properties for XTheadVector extension [04/65] target/riscv: Override some csr ops for XTheadVector [05/65] target/riscv: Add mlen in DisasContext [06/65] target/riscv: Implement insns decode rules for XTheadVector [07/65] target/riscv: implement th.vsetvl{i} for XTheadVector [08/65] target/riscv: Add strided load instructions for XTheadVector [09/65] target/riscv: Add strided store instructions for XTheadVector [10/65] target/riscv: Add unit-stride load instructions for XTheadVector [11/65] target/riscv: Add unit-stride store instructions for XTheadVector [12/65] target/riscv: Add indexed load instructions for XTheadVector [13/65] target/riscv: Add indexed store instructions for XTheadVector [14/65] target/riscv: Add unit-stride fault-only-first instructions for XTheadVector [15/65] target/riscv: Add vector amo operations for XTheadVector [16/65] target/riscv: Add single-width integer add and subtract instructions for XTheadVector [17/65] target/riscv: Add widening integer add/subtract instructions for XTheadVector [18/65] target/riscv: Add integer add-with-carry/sub-with-borrow instructions for XTheadVector [19/65] target/riscv: Add bitwise logical instructions for XTheadVector [20/65] target/riscv: Add single-width bit shift instructions for XTheadVector [21/65] target/riscv: Add narrowing integer right shift instructions for XTheadVector [22/65] target/riscv: Add integer compare instructions for XTheadVector [23/65] target/riscv: Add integer min/max instructions for XTheadVector [24/65] target/riscv: Add single-width integer multiply instructions for XTheadVector [25/65] target/riscv: Add integer divide instructions for XTheadVector [26/65] target/riscv: Add widening integer multiply instructions for XTheadVector [27/65] target/riscv: Add single-width integer multiply-add instructions for XTheadVector [28/65] target/riscv: Add widening integer multiply-add instructions for XTheadVector [29/65] target/riscv: Add integer merge and move instructions for XTheadVector [30/65] target/riscv: Add single-width saturating add and sub instructions for XTheadVector [31/65] target/riscv: Add single-width average add and sub instructions for XTheadVector [32/65] target/riscv: Add single-width fractional mul with rounding and saturation for XTheadVector [33/65] target/riscv: Add widening saturating scaled multiply-add instructions for XTheadVector [34/65] target/riscv: Add single-width scaling shift instructions for XTheadVector [35/65] target/riscv: Add narrowing fixed-point clip instructions for XTheadVector [36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector [37/65] target/riscv: Add widening floating-point add/sub instructions for XTheadVector [38/65] target/riscv: Add single-width floating-point multiply/divide instructions for XTheadVector [39/65] target/riscv: Add widening floating-point multiply instructions for XTheadVector [40/65] target/riscv: Add single-width floating-point fused multiply-add instructions for XTheadVec… [41/65] target/riscv: Add widening floating-point fused mul-add instructions for XTheadVector [42/65] target/riscv: Add floating-pointing square-root instructions for XTheadVector [43/65] target/riscv: Add floating-point MIN/MAX instructions for XTheadVector [44/65] target/riscv: Add floating-point sign-injection instructions for XTheadVector [45/65] target/riscv: Add floating-point compare instructions for XTheadVector [46/65] target/riscv: Add floating-point classify and merge instructions for XTheadVector [47/65] target/riscv: Add single-width floating-point/integer type-convert instructions for XTheadV… [48/65] target/riscv: Add widening floating-point/integer type-convert instructions for XTheadVector [49/65] target/riscv: Add narrowing floating-point/integer type-convert instructions for XTheadVect… [50/65] target/riscv: Add single-width integer reduction instructions for XTheadVector [51/65] target/riscv: Add widening integer reduction instructions for XTheadVector [52/65] target/riscv: Add single-width floating-point reduction instructions for XTheadVector [53/65] target/riscv: Add widening floating-point reduction instructions for XTheadVector [54/65] target/riscv: Add mask-register logical instructions for XTheadVector [55/65] target/riscv: Add vector mask population count vmpopc for XTheadVector [56/65] target/riscv: Add th.vmfirst.m for XTheadVector [57/65] target/riscv: Add set-X-first mask bit instructrions for XTheadVector [58/65] target/riscv: Add vector iota instruction for XTheadVector [59/65] target/riscv: Add vector element index instruction for XTheadVector [60/65] target/riscv: Add integer extract and scalar move instructions for XTheadVector [61/65] target/riscv: Add floating-point scalar move instructions for XTheadVector [62/65] target/riscv: Add vector slide instructions for XTheadVector [63/65] target/riscv: Add vector register gather instructions for XTheadVector [64/65] target/riscv: Add vector compress instruction for XTheadVector [65/65] target/riscv: Enable XTheadVector extension for c906

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8d0b500758..6558e652df 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -813,6 +813,42 @@ void riscv_add_satp_mode_properties(Object *obj); bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); /* CSR function table */ +RISCVException fs(CPURISCVState *env, int csrno); +RISCVException vs(CPURISCVState *env, int csrno); +RISCVException any(CPURISCVState *env, int csrno); +RISCVException smode(CPURISCVState *env, int csrno); +RISCVException read_fcsr(CPURISCVState *env, int csrno, + target_ulong *val); +RISCVException write_fcsr(CPURISCVState *env, int csrno, + target_ulong val); +RISCVException read_vtype(CPURISCVState *env, int csrno, + target_ulong *val); +RISCVException read_vl(CPURISCVState *env, int csrno, + target_ulong *val); +RISCVException read_vlenb(CPURISCVState *env, int csrno, + target_ulong *val); +RISCVException read_vxrm(CPURISCVState *env, int csrno, + target_ulong *val); +RISCVException write_vxrm(CPURISCVState *env, int csrno, + target_ulong val); +RISCVException read_vxsat(CPURISCVState *env, int csrno, + target_ulong *val); +RISCVException write_vxsat(CPURISCVState *env, int csrno, + target_ulong val); +RISCVException read_vstart(CPURISCVState *env, int csrno, + target_ulong *val); +RISCVException write_vstart(CPURISCVState *env, int csrno, + target_ulong val); +RISCVException read_mstatus(CPURISCVState *env, int csrno, + target_ulong *val); +RISCVException write_mstatus(CPURISCVState *env, int csrno, + target_ulong val); +RISCVException write_sstatus(CPURISCVState *env, int csrno, + target_ulong val); +RISCVException read_sstatus(CPURISCVState *env, int csrno, + target_ulong *val); +RISCVException read_vcsr(CPURISCVState *env, int csrno, target_ulong *val); +RISCVException write_vcsr(CPURISCVState *env, int csrno, target_ulong val); extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fc2068ee4d..5a5e0ed444 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -904,4 +904,22 @@ typedef enum RISCVException { #define MCONTEXT64 0x0000000000001FFFULL #define MCONTEXT32_HCONTEXT 0x0000007F #define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL + +/* Xuantie custom CSRs */ +#define TH_MSTATUS_VS 0x01800000 + +#define TH_FSR_VXRM_SHIFT 9 +#define TH_FSR_VXRM (0x3 << TH_FSR_VXRM_SHIFT) + +#define TH_FSR_VXSAT_SHIFT 8 +#define TH_FSR_VXSAT (0x1 << TH_FSR_VXSAT_SHIFT) + +#define TH_VTYPE_LMUL_SHIFT 0 +#define TH_VTYPE_LMUL (0x3 << TH_VTYPE_LMUL_SHIFT) + +#define TH_VTYPE_SEW_SHIFT 2 +#define TH_VTYPE_SEW (0x7 << TH_VTYPE_SEW_SHIFT) + +#define TH_VTYPE_CLEAR_SHIFT 5 +#define TH_VTYPE_CLEAR (0x7 << TH_VTYPE_CLEAR_SHIFT) #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 726096444f..797929d5b9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -76,7 +76,7 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) } #endif -static RISCVException fs(CPURISCVState *env, int csrno) +RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env) && @@ -91,7 +91,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) return RISCV_EXCP_NONE; } -static RISCVException vs(CPURISCVState *env, int csrno) +RISCVException vs(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->ext_zve32f) { #if !defined(CONFIG_USER_ONLY) @@ -227,7 +227,7 @@ static RISCVException sscofpmf(CPURISCVState *env, int csrno) return RISCV_EXCP_NONE; } -static RISCVException any(CPURISCVState *env, int csrno) +RISCVException any(CPURISCVState *env, int csrno) { return RISCV_EXCP_NONE; } @@ -260,7 +260,7 @@ static RISCVException aia_any32(CPURISCVState *env, int csrno) return any32(env, csrno); } -static RISCVException smode(CPURISCVState *env, int csrno) +RISCVException smode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS)) { return RISCV_EXCP_NONE; @@ -635,7 +635,7 @@ static RISCVException write_frm(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException read_fcsr(CPURISCVState *env, int csrno, +RISCVException read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) @@ -643,7 +643,7 @@ static RISCVException read_fcsr(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException write_fcsr(CPURISCVState *env, int csrno, +RISCVException write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) @@ -656,7 +656,7 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException read_vtype(CPURISCVState *env, int csrno, +RISCVException read_vtype(CPURISCVState *env, int csrno, target_ulong *val) { uint64_t vill; @@ -674,28 +674,28 @@ static RISCVException read_vtype(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException read_vl(CPURISCVState *env, int csrno, +RISCVException read_vl(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->vl; return RISCV_EXCP_NONE; } -static RISCVException read_vlenb(CPURISCVState *env, int csrno, +RISCVException read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) { *val = riscv_cpu_cfg(env)->vlenb; return RISCV_EXCP_NONE; } -static RISCVException read_vxrm(CPURISCVState *env, int csrno, +RISCVException read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->vxrm; return RISCV_EXCP_NONE; } -static RISCVException write_vxrm(CPURISCVState *env, int csrno, +RISCVException write_vxrm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) @@ -705,14 +705,14 @@ static RISCVException write_vxrm(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException read_vxsat(CPURISCVState *env, int csrno, +RISCVException read_vxsat(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->vxsat; return RISCV_EXCP_NONE; } -static RISCVException write_vxsat(CPURISCVState *env, int csrno, +RISCVException write_vxsat(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) @@ -722,14 +722,14 @@ static RISCVException write_vxsat(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException read_vstart(CPURISCVState *env, int csrno, +RISCVException read_vstart(CPURISCVState *env, int csrno, target_ulong *val) { *val = env->vstart; return RISCV_EXCP_NONE; } -static RISCVException write_vstart(CPURISCVState *env, int csrno, +RISCVException write_vstart(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) @@ -743,14 +743,14 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException read_vcsr(CPURISCVState *env, int csrno, +RISCVException read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) { *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); return RISCV_EXCP_NONE; } -static RISCVException write_vcsr(CPURISCVState *env, int csrno, +RISCVException write_vcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) @@ -1286,7 +1286,7 @@ static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) return status; } -static RISCVException read_mstatus(CPURISCVState *env, int csrno, +RISCVException read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) { *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); @@ -1351,7 +1351,7 @@ static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp, return val; } -static RISCVException write_mstatus(CPURISCVState *env, int csrno, +RISCVException write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { uint64_t mstatus = env->mstatus; @@ -2639,7 +2639,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException read_sstatus(CPURISCVState *env, int csrno, +RISCVException read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { target_ulong mask = (sstatus_v1_10_mask); @@ -2651,7 +2651,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException write_sstatus(CPURISCVState *env, int csrno, +RISCVException write_sstatus(CPURISCVState *env, int csrno, target_ulong val) { target_ulong mask = (sstatus_v1_10_mask); diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c index dc087b1ffa..4fc488fc10 100644 --- a/target/riscv/th_csr.c +++ b/target/riscv/th_csr.c @@ -41,7 +41,124 @@ static int test_thead_mvendorid(RISCVCPU *cpu) return 0; } +/* + * In XTheadVector, vcsr is inaccessible + * and we just check ext_xtheadvector instead of ext_zve32f + */ +static RISCVException th_vs(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu = env_archcpu(env); + if (cpu->cfg.ext_xtheadvector) { + if (csrno == CSR_VCSR) { + return RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; + } + return vs(env, csrno); +} + +static RISCVException +th_read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) +{ + RISCVCPU *cpu = env_archcpu(env); + RISCVException ret = read_fcsr(env, csrno, val); + if (cpu->cfg.ext_xtheadvector) { + *val = set_field(*val, TH_FSR_VXRM, env->vxrm); + *val = set_field(*val, TH_FSR_VXSAT, env->vxsat); + } + return ret; +} + +static RISCVException +th_write_fcsr(CPURISCVState *env, int csrno, target_ulong val) +{ + RISCVCPU *cpu = env_archcpu(env); + if (cpu->cfg.ext_xtheadvector) { + env->vxrm = get_field(val, TH_FSR_VXRM); + env->vxsat = get_field(val, TH_FSR_VXSAT); + } + return write_fcsr(env, csrno, val); +} + +/* + * We use the RVV1.0 format for env->vtype + * When reading vtype, we need to change the format. + * In RVV1.0: + * vtype[7] -> vma + * vtype[6] -> vta + * vtype[5:3] -> vsew + * vtype[2:0] -> vlmul + * In XTheadVector: + * vtype[6:5] -> vediv + * vtype[4:2] -> vsew + * vtype[1:0] -> vlmul + * Although vlmul size is different between RVV1.0 and XTheadVector, + * the lower 2 bits have the same meaning. + * vma, vta and vediv are useless in XTheadVector, So we need to clear + * vtype[7:5] for XTheadVector + */ +static RISCVException +th_read_vtype(CPURISCVState *env, int csrno, target_ulong *val) +{ + RISCVCPU *cpu = env_archcpu(env); + RISCVException ret = read_vtype(env, csrno, val); + if (cpu->cfg.ext_xtheadvector) { + *val = set_field(*val, TH_VTYPE_LMUL, + FIELD_EX64(*val, VTYPE, VLMUL)); + *val = set_field(*val, TH_VTYPE_SEW, + FIELD_EX64(*val, VTYPE, VSEW)); + *val = set_field(*val, TH_VTYPE_CLEAR, 0); + } + return ret; +} + #if !defined(CONFIG_USER_ONLY) +static RISCVException +th_read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + RISCVCPU *cpu = env_archcpu(env); + RISCVException ret = read_mstatus(env, csrno, val); + if (cpu->cfg.ext_xtheadvector) { + *val = set_field(*val, TH_MSTATUS_VS, + get_field(*val, MSTATUS_VS)); + } + return ret; +} + +static RISCVException +th_write_mstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + RISCVCPU *cpu = env_archcpu(env); + if (cpu->cfg.ext_xtheadvector) { + val = set_field(val, MSTATUS_VS, + get_field(val, TH_MSTATUS_VS)); + } + return write_mstatus(env, csrno, val); +} + +static RISCVException +th_read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + RISCVCPU *cpu = env_archcpu(env); + RISCVException ret = read_sstatus(env, csrno, val); + if (cpu->cfg.ext_xtheadvector) { + *val = set_field(*val, TH_MSTATUS_VS, + get_field(*val, MSTATUS_VS)); + } + return ret; +} + +static RISCVException +th_write_sstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + RISCVCPU *cpu = env_archcpu(env); + if (cpu->cfg.ext_xtheadvector) { + val = set_field(val, MSTATUS_VS, + get_field(val, TH_MSTATUS_VS)); + } + return write_sstatus(env, csrno, val); +} + static RISCVException s_mode_csr(CPURISCVState *env, int csrno) { if (env->debugger) @@ -63,13 +180,63 @@ static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno, #endif static riscv_csr th_csr_list[] = { + { + .csrno = CSR_FCSR, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "fcsr", fs, th_read_fcsr, th_write_fcsr } + }, + { + .csrno = CSR_VSTART, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "vstart", th_vs, read_vstart, write_vstart } + }, + { + .csrno = CSR_VXSAT, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "vxsat", th_vs, read_vxsat, write_vxsat } + }, + { + .csrno = CSR_VXRM, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "vxrm", th_vs, read_vxrm, write_vxrm } + }, + { + .csrno = CSR_VCSR, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "vcsr", th_vs, read_vcsr, write_vcsr } + }, + { + .csrno = CSR_VL, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "vl", th_vs, read_vl} + }, + { + .csrno = CSR_VTYPE, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "vtype", th_vs, th_read_vtype} + }, + { + .csrno = CSR_VLENB, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "vlenb", th_vs, read_vlenb} + }, #if !defined(CONFIG_USER_ONLY) + { + .csrno = CSR_MSTATUS, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "mstatus", any, th_read_mstatus, th_write_mstatus} + }, + { + .csrno = CSR_SSTATUS, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "sstatus", smode, th_read_sstatus, th_write_sstatus} + }, { .csrno = CSR_TH_SXSTATUS, .insertion_test = test_thead_mvendorid, .csr_ops = { "th.sxstatus", s_mode_csr, read_th_sxstatus } }, -#endif +#endif /* !CONFIG_USER_ONLY */ }; void th_register_custom_csrs(RISCVCPU *cpu)

[04/65] target/riscv: Override some csr ops for XTheadVector

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Patch