[22/65] target/riscv: Add integer compare instructions for XTheadVector

Message ID	20240412073735.76413-23-eric.huang@linux.alibaba.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Huang Tao <eric.huang@linux.alibaba.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, Huang Tao <eric.huang@linux.alibaba.com> Subject: [PATCH 22/65] target/riscv: Add integer compare instructions for XTheadVector Date: Fri, 12 Apr 2024 15:36:52 +0800 Message-ID: <20240412073735.76413-23-eric.huang@linux.alibaba.com> In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com> References: <20240412073735.76413-1-eric.huang@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=115.124.30.133; envelope-from=eric.huang@linux.alibaba.com; helo=out30-133.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	target/riscv: Support XTheadVector extension \| expand [00/65] target/riscv: Support XTheadVector extension [01/65] riscv: thead: Add th.sxstatus CSR emulation [02/65] target/riscv: Reuse th_csr.c to add user-mode csrs [03/65] target/riscv: Add properties for XTheadVector extension [04/65] target/riscv: Override some csr ops for XTheadVector [05/65] target/riscv: Add mlen in DisasContext [06/65] target/riscv: Implement insns decode rules for XTheadVector [07/65] target/riscv: implement th.vsetvl{i} for XTheadVector [08/65] target/riscv: Add strided load instructions for XTheadVector [09/65] target/riscv: Add strided store instructions for XTheadVector [10/65] target/riscv: Add unit-stride load instructions for XTheadVector [11/65] target/riscv: Add unit-stride store instructions for XTheadVector [12/65] target/riscv: Add indexed load instructions for XTheadVector [13/65] target/riscv: Add indexed store instructions for XTheadVector [14/65] target/riscv: Add unit-stride fault-only-first instructions for XTheadVector [15/65] target/riscv: Add vector amo operations for XTheadVector [16/65] target/riscv: Add single-width integer add and subtract instructions for XTheadVector [17/65] target/riscv: Add widening integer add/subtract instructions for XTheadVector [18/65] target/riscv: Add integer add-with-carry/sub-with-borrow instructions for XTheadVector [19/65] target/riscv: Add bitwise logical instructions for XTheadVector [20/65] target/riscv: Add single-width bit shift instructions for XTheadVector [21/65] target/riscv: Add narrowing integer right shift instructions for XTheadVector [22/65] target/riscv: Add integer compare instructions for XTheadVector [23/65] target/riscv: Add integer min/max instructions for XTheadVector [24/65] target/riscv: Add single-width integer multiply instructions for XTheadVector [25/65] target/riscv: Add integer divide instructions for XTheadVector [26/65] target/riscv: Add widening integer multiply instructions for XTheadVector [27/65] target/riscv: Add single-width integer multiply-add instructions for XTheadVector [28/65] target/riscv: Add widening integer multiply-add instructions for XTheadVector [29/65] target/riscv: Add integer merge and move instructions for XTheadVector [30/65] target/riscv: Add single-width saturating add and sub instructions for XTheadVector [31/65] target/riscv: Add single-width average add and sub instructions for XTheadVector [32/65] target/riscv: Add single-width fractional mul with rounding and saturation for XTheadVector [33/65] target/riscv: Add widening saturating scaled multiply-add instructions for XTheadVector [34/65] target/riscv: Add single-width scaling shift instructions for XTheadVector [35/65] target/riscv: Add narrowing fixed-point clip instructions for XTheadVector [36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector [37/65] target/riscv: Add widening floating-point add/sub instructions for XTheadVector [38/65] target/riscv: Add single-width floating-point multiply/divide instructions for XTheadVector [39/65] target/riscv: Add widening floating-point multiply instructions for XTheadVector [40/65] target/riscv: Add single-width floating-point fused multiply-add instructions for XTheadVec… [41/65] target/riscv: Add widening floating-point fused mul-add instructions for XTheadVector [42/65] target/riscv: Add floating-pointing square-root instructions for XTheadVector [43/65] target/riscv: Add floating-point MIN/MAX instructions for XTheadVector [44/65] target/riscv: Add floating-point sign-injection instructions for XTheadVector [45/65] target/riscv: Add floating-point compare instructions for XTheadVector [46/65] target/riscv: Add floating-point classify and merge instructions for XTheadVector [47/65] target/riscv: Add single-width floating-point/integer type-convert instructions for XTheadV… [48/65] target/riscv: Add widening floating-point/integer type-convert instructions for XTheadVector [49/65] target/riscv: Add narrowing floating-point/integer type-convert instructions for XTheadVect… [50/65] target/riscv: Add single-width integer reduction instructions for XTheadVector [51/65] target/riscv: Add widening integer reduction instructions for XTheadVector [52/65] target/riscv: Add single-width floating-point reduction instructions for XTheadVector [53/65] target/riscv: Add widening floating-point reduction instructions for XTheadVector [54/65] target/riscv: Add mask-register logical instructions for XTheadVector [55/65] target/riscv: Add vector mask population count vmpopc for XTheadVector [56/65] target/riscv: Add th.vmfirst.m for XTheadVector [57/65] target/riscv: Add set-X-first mask bit instructrions for XTheadVector [58/65] target/riscv: Add vector iota instruction for XTheadVector [59/65] target/riscv: Add vector element index instruction for XTheadVector [60/65] target/riscv: Add integer extract and scalar move instructions for XTheadVector [61/65] target/riscv: Add floating-point scalar move instructions for XTheadVector [62/65] target/riscv: Add vector slide instructions for XTheadVector [63/65] target/riscv: Add vector register gather instructions for XTheadVector [64/65] target/riscv: Add vector compress instruction for XTheadVector [65/65] target/riscv: Enable XTheadVector extension for c906

diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d3170ba91f..8f2dec158b 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1638,3 +1638,60 @@ DEF_HELPER_6(th_vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(th_vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmseq_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmseq_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsne_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsne_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsne_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsne_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsltu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsltu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsltu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsltu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmslt_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmslt_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmslt_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmslt_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsleu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsleu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsleu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsleu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsle_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsle_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsle_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmsle_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmseq_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmseq_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmseq_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmseq_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsne_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsne_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsne_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsne_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsltu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsltu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsltu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsltu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmslt_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmslt_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmslt_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmslt_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsleu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsleu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsleu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsleu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsle_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsle_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsle_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsle_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsgtu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsgtu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsgtu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsgtu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsgt_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsgt_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsgt_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmsgt_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc index 68810ff0ec..049d9da0a5 100644 --- a/target/riscv/insn_trans/trans_xtheadvector.c.inc +++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc @@ -1470,32 +1470,61 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ GEN_OPIVI_NARROW_TRANS_TH(th_vnsra_vi, IMM_ZX, th_vnsra_vx) GEN_OPIVI_NARROW_TRANS_TH(th_vnsrl_vi, IMM_ZX, th_vnsrl_vx) +/* Vector Integer Comparison Instructions */ + +/* + * For all comparison instructions, an illegal instruction exception is raised + * if the destination vector register overlaps a source vector register group + * and LMUL > 1. + */ +static bool opivv_cmp_check_th(DisasContext *s, arg_rmrr *a) +{ + return (require_xtheadvector(s) && + vext_check_isa_ill(s) && + th_check_reg(s, a->rs2, false) && + th_check_reg(s, a->rs1, false) && + ((th_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && + th_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || + (s->lmul == 0))); +} +GEN_OPIVV_TRANS_TH(th_vmseq_vv, opivv_cmp_check_th) +GEN_OPIVV_TRANS_TH(th_vmsne_vv, opivv_cmp_check_th) +GEN_OPIVV_TRANS_TH(th_vmsltu_vv, opivv_cmp_check_th) +GEN_OPIVV_TRANS_TH(th_vmslt_vv, opivv_cmp_check_th) +GEN_OPIVV_TRANS_TH(th_vmsleu_vv, opivv_cmp_check_th) +GEN_OPIVV_TRANS_TH(th_vmsle_vv, opivv_cmp_check_th) + +static bool opivx_cmp_check_th(DisasContext *s, arg_rmrr *a) +{ + return (require_xtheadvector(s) && + vext_check_isa_ill(s) && + th_check_reg(s, a->rs2, false) && + (th_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || + (s->lmul == 0))); +} + +GEN_OPIVX_TRANS_TH(th_vmseq_vx, opivx_cmp_check_th) +GEN_OPIVX_TRANS_TH(th_vmsne_vx, opivx_cmp_check_th) +GEN_OPIVX_TRANS_TH(th_vmsltu_vx, opivx_cmp_check_th) +GEN_OPIVX_TRANS_TH(th_vmslt_vx, opivx_cmp_check_th) +GEN_OPIVX_TRANS_TH(th_vmsleu_vx, opivx_cmp_check_th) +GEN_OPIVX_TRANS_TH(th_vmsle_vx, opivx_cmp_check_th) +GEN_OPIVX_TRANS_TH(th_vmsgtu_vx, opivx_cmp_check_th) +GEN_OPIVX_TRANS_TH(th_vmsgt_vx, opivx_cmp_check_th) + +GEN_OPIVI_TRANS_TH(th_vmseq_vi, IMM_SX, th_vmseq_vx, opivx_cmp_check_th) +GEN_OPIVI_TRANS_TH(th_vmsne_vi, IMM_SX, th_vmsne_vx, opivx_cmp_check_th) +GEN_OPIVI_TRANS_TH(th_vmsleu_vi, IMM_ZX, th_vmsleu_vx, opivx_cmp_check_th) +GEN_OPIVI_TRANS_TH(th_vmsle_vi, IMM_SX, th_vmsle_vx, opivx_cmp_check_th) +GEN_OPIVI_TRANS_TH(th_vmsgtu_vi, IMM_ZX, th_vmsgtu_vx, opivx_cmp_check_th) +GEN_OPIVI_TRANS_TH(th_vmsgt_vi, IMM_SX, th_vmsgt_vx, opivx_cmp_check_th) + #define TH_TRANS_STUB(NAME) \ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { \ return require_xtheadvector(s); \ } -TH_TRANS_STUB(th_vmseq_vv) -TH_TRANS_STUB(th_vmseq_vx) -TH_TRANS_STUB(th_vmseq_vi) -TH_TRANS_STUB(th_vmsne_vv) -TH_TRANS_STUB(th_vmsne_vx) -TH_TRANS_STUB(th_vmsne_vi) -TH_TRANS_STUB(th_vmsltu_vv) -TH_TRANS_STUB(th_vmsltu_vx) -TH_TRANS_STUB(th_vmslt_vv) -TH_TRANS_STUB(th_vmslt_vx) -TH_TRANS_STUB(th_vmsleu_vv) -TH_TRANS_STUB(th_vmsleu_vx) -TH_TRANS_STUB(th_vmsleu_vi) -TH_TRANS_STUB(th_vmsle_vv) -TH_TRANS_STUB(th_vmsle_vx) -TH_TRANS_STUB(th_vmsle_vi) -TH_TRANS_STUB(th_vmsgtu_vx) -TH_TRANS_STUB(th_vmsgtu_vi) -TH_TRANS_STUB(th_vmsgt_vx) -TH_TRANS_STUB(th_vmsgt_vi) TH_TRANS_STUB(th_vminu_vv) TH_TRANS_STUB(th_vminu_vx) TH_TRANS_STUB(th_vmin_vv) diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c index f4bd80349d..827650b325 100644 --- a/target/riscv/xtheadvector_helper.c +++ b/target/riscv/xtheadvector_helper.c @@ -1415,3 +1415,130 @@ GEN_TH_SHIFT_VX(th_vnsra_vx_h, int16_t, int32_t, H2, H4, TH_SRL, 0x1f, clearh_th) GEN_TH_SHIFT_VX(th_vnsra_vx_w, int32_t, int64_t, H4, H8, TH_SRL, 0x3f, clearl_th) + +/* Vector Integer Comparison Instructions */ +#define TH_MSEQ(N, M) (N == M) +#define TH_MSNE(N, M) (N != M) +#define TH_MSLT(N, M) (N < M) +#define TH_MSLE(N, M) (N <= M) +#define TH_MSGT(N, M) (N > M) + +#define GEN_TH_CMP_VV(NAME, ETYPE, H, DO_OP) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = th_mlen(desc); \ + uint32_t vm = th_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t vlmax = th_maxsz(desc) / sizeof(ETYPE); \ + uint32_t i; \ + \ + VSTART_CHECK_EARLY_EXIT(env); \ + for (i = env->vstart; i < vl; i++) { \ + ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ + if (!vm && !th_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + th_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \ + } \ + env->vstart = 0; \ + for (; i < vlmax; i++) { \ + th_set_elem_mask(vd, mlen, i, 0); \ + } \ +} + +GEN_TH_CMP_VV(th_vmseq_vv_b, uint8_t, H1, TH_MSEQ) +GEN_TH_CMP_VV(th_vmseq_vv_h, uint16_t, H2, TH_MSEQ) +GEN_TH_CMP_VV(th_vmseq_vv_w, uint32_t, H4, TH_MSEQ) +GEN_TH_CMP_VV(th_vmseq_vv_d, uint64_t, H8, TH_MSEQ) + +GEN_TH_CMP_VV(th_vmsne_vv_b, uint8_t, H1, TH_MSNE) +GEN_TH_CMP_VV(th_vmsne_vv_h, uint16_t, H2, TH_MSNE) +GEN_TH_CMP_VV(th_vmsne_vv_w, uint32_t, H4, TH_MSNE) +GEN_TH_CMP_VV(th_vmsne_vv_d, uint64_t, H8, TH_MSNE) + +GEN_TH_CMP_VV(th_vmsltu_vv_b, uint8_t, H1, TH_MSLT) +GEN_TH_CMP_VV(th_vmsltu_vv_h, uint16_t, H2, TH_MSLT) +GEN_TH_CMP_VV(th_vmsltu_vv_w, uint32_t, H4, TH_MSLT) +GEN_TH_CMP_VV(th_vmsltu_vv_d, uint64_t, H8, TH_MSLT) + +GEN_TH_CMP_VV(th_vmslt_vv_b, int8_t, H1, TH_MSLT) +GEN_TH_CMP_VV(th_vmslt_vv_h, int16_t, H2, TH_MSLT) +GEN_TH_CMP_VV(th_vmslt_vv_w, int32_t, H4, TH_MSLT) +GEN_TH_CMP_VV(th_vmslt_vv_d, int64_t, H8, TH_MSLT) + +GEN_TH_CMP_VV(th_vmsleu_vv_b, uint8_t, H1, TH_MSLE) +GEN_TH_CMP_VV(th_vmsleu_vv_h, uint16_t, H2, TH_MSLE) +GEN_TH_CMP_VV(th_vmsleu_vv_w, uint32_t, H4, TH_MSLE) +GEN_TH_CMP_VV(th_vmsleu_vv_d, uint64_t, H8, TH_MSLE) + +GEN_TH_CMP_VV(th_vmsle_vv_b, int8_t, H1, TH_MSLE) +GEN_TH_CMP_VV(th_vmsle_vv_h, int16_t, H2, TH_MSLE) +GEN_TH_CMP_VV(th_vmsle_vv_w, int32_t, H4, TH_MSLE) +GEN_TH_CMP_VV(th_vmsle_vv_d, int64_t, H8, TH_MSLE) + +#define GEN_TH_CMP_VX(NAME, ETYPE, H, DO_OP) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = th_mlen(desc); \ + uint32_t vm = th_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t vlmax = th_maxsz(desc) / sizeof(ETYPE); \ + uint32_t i; \ + \ + VSTART_CHECK_EARLY_EXIT(env); \ + for (i = env->vstart; i < vl; i++) { \ + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ + if (!vm && !th_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + th_set_elem_mask(vd, mlen, i, \ + DO_OP(s2, (ETYPE)(target_long)s1)); \ + } \ + env->vstart = 0; \ + for (; i < vlmax; i++) { \ + th_set_elem_mask(vd, mlen, i, 0); \ + } \ +} + +GEN_TH_CMP_VX(th_vmseq_vx_b, uint8_t, H1, TH_MSEQ) +GEN_TH_CMP_VX(th_vmseq_vx_h, uint16_t, H2, TH_MSEQ) +GEN_TH_CMP_VX(th_vmseq_vx_w, uint32_t, H4, TH_MSEQ) +GEN_TH_CMP_VX(th_vmseq_vx_d, uint64_t, H8, TH_MSEQ) + +GEN_TH_CMP_VX(th_vmsne_vx_b, uint8_t, H1, TH_MSNE) +GEN_TH_CMP_VX(th_vmsne_vx_h, uint16_t, H2, TH_MSNE) +GEN_TH_CMP_VX(th_vmsne_vx_w, uint32_t, H4, TH_MSNE) +GEN_TH_CMP_VX(th_vmsne_vx_d, uint64_t, H8, TH_MSNE) + +GEN_TH_CMP_VX(th_vmsltu_vx_b, uint8_t, H1, TH_MSLT) +GEN_TH_CMP_VX(th_vmsltu_vx_h, uint16_t, H2, TH_MSLT) +GEN_TH_CMP_VX(th_vmsltu_vx_w, uint32_t, H4, TH_MSLT) +GEN_TH_CMP_VX(th_vmsltu_vx_d, uint64_t, H8, TH_MSLT) + +GEN_TH_CMP_VX(th_vmslt_vx_b, int8_t, H1, TH_MSLT) +GEN_TH_CMP_VX(th_vmslt_vx_h, int16_t, H2, TH_MSLT) +GEN_TH_CMP_VX(th_vmslt_vx_w, int32_t, H4, TH_MSLT) +GEN_TH_CMP_VX(th_vmslt_vx_d, int64_t, H8, TH_MSLT) + +GEN_TH_CMP_VX(th_vmsleu_vx_b, uint8_t, H1, TH_MSLE) +GEN_TH_CMP_VX(th_vmsleu_vx_h, uint16_t, H2, TH_MSLE) +GEN_TH_CMP_VX(th_vmsleu_vx_w, uint32_t, H4, TH_MSLE) +GEN_TH_CMP_VX(th_vmsleu_vx_d, uint64_t, H8, TH_MSLE) + +GEN_TH_CMP_VX(th_vmsle_vx_b, int8_t, H1, TH_MSLE) +GEN_TH_CMP_VX(th_vmsle_vx_h, int16_t, H2, TH_MSLE) +GEN_TH_CMP_VX(th_vmsle_vx_w, int32_t, H4, TH_MSLE) +GEN_TH_CMP_VX(th_vmsle_vx_d, int64_t, H8, TH_MSLE) + +GEN_TH_CMP_VX(th_vmsgtu_vx_b, uint8_t, H1, TH_MSGT) +GEN_TH_CMP_VX(th_vmsgtu_vx_h, uint16_t, H2, TH_MSGT) +GEN_TH_CMP_VX(th_vmsgtu_vx_w, uint32_t, H4, TH_MSGT) +GEN_TH_CMP_VX(th_vmsgtu_vx_d, uint64_t, H8, TH_MSGT) + +GEN_TH_CMP_VX(th_vmsgt_vx_b, int8_t, H1, TH_MSGT) +GEN_TH_CMP_VX(th_vmsgt_vx_h, int16_t, H2, TH_MSGT) +GEN_TH_CMP_VX(th_vmsgt_vx_w, int32_t, H4, TH_MSGT) +GEN_TH_CMP_VX(th_vmsgt_vx_d, int64_t, H8, TH_MSGT)

[22/65] target/riscv: Add integer compare instructions for XTheadVector

Commit Message

Patch