[36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector

Message ID	20240412073735.76413-37-eric.huang@linux.alibaba.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Huang Tao <eric.huang@linux.alibaba.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, Huang Tao <eric.huang@linux.alibaba.com> Subject: [PATCH 36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector Date: Fri, 12 Apr 2024 15:37:06 +0800 Message-ID: <20240412073735.76413-37-eric.huang@linux.alibaba.com> In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com> References: <20240412073735.76413-1-eric.huang@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=115.124.30.133; envelope-from=eric.huang@linux.alibaba.com; helo=out30-133.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	target/riscv: Support XTheadVector extension \| expand [00/65] target/riscv: Support XTheadVector extension [01/65] riscv: thead: Add th.sxstatus CSR emulation [02/65] target/riscv: Reuse th_csr.c to add user-mode csrs [03/65] target/riscv: Add properties for XTheadVector extension [04/65] target/riscv: Override some csr ops for XTheadVector [05/65] target/riscv: Add mlen in DisasContext [06/65] target/riscv: Implement insns decode rules for XTheadVector [07/65] target/riscv: implement th.vsetvl{i} for XTheadVector [08/65] target/riscv: Add strided load instructions for XTheadVector [09/65] target/riscv: Add strided store instructions for XTheadVector [10/65] target/riscv: Add unit-stride load instructions for XTheadVector [11/65] target/riscv: Add unit-stride store instructions for XTheadVector [12/65] target/riscv: Add indexed load instructions for XTheadVector [13/65] target/riscv: Add indexed store instructions for XTheadVector [14/65] target/riscv: Add unit-stride fault-only-first instructions for XTheadVector [15/65] target/riscv: Add vector amo operations for XTheadVector [16/65] target/riscv: Add single-width integer add and subtract instructions for XTheadVector [17/65] target/riscv: Add widening integer add/subtract instructions for XTheadVector [18/65] target/riscv: Add integer add-with-carry/sub-with-borrow instructions for XTheadVector [19/65] target/riscv: Add bitwise logical instructions for XTheadVector [20/65] target/riscv: Add single-width bit shift instructions for XTheadVector [21/65] target/riscv: Add narrowing integer right shift instructions for XTheadVector [22/65] target/riscv: Add integer compare instructions for XTheadVector [23/65] target/riscv: Add integer min/max instructions for XTheadVector [24/65] target/riscv: Add single-width integer multiply instructions for XTheadVector [25/65] target/riscv: Add integer divide instructions for XTheadVector [26/65] target/riscv: Add widening integer multiply instructions for XTheadVector [27/65] target/riscv: Add single-width integer multiply-add instructions for XTheadVector [28/65] target/riscv: Add widening integer multiply-add instructions for XTheadVector [29/65] target/riscv: Add integer merge and move instructions for XTheadVector [30/65] target/riscv: Add single-width saturating add and sub instructions for XTheadVector [31/65] target/riscv: Add single-width average add and sub instructions for XTheadVector [32/65] target/riscv: Add single-width fractional mul with rounding and saturation for XTheadVector [33/65] target/riscv: Add widening saturating scaled multiply-add instructions for XTheadVector [34/65] target/riscv: Add single-width scaling shift instructions for XTheadVector [35/65] target/riscv: Add narrowing fixed-point clip instructions for XTheadVector [36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector [37/65] target/riscv: Add widening floating-point add/sub instructions for XTheadVector [38/65] target/riscv: Add single-width floating-point multiply/divide instructions for XTheadVector [39/65] target/riscv: Add widening floating-point multiply instructions for XTheadVector [40/65] target/riscv: Add single-width floating-point fused multiply-add instructions for XTheadVec… [41/65] target/riscv: Add widening floating-point fused mul-add instructions for XTheadVector [42/65] target/riscv: Add floating-pointing square-root instructions for XTheadVector [43/65] target/riscv: Add floating-point MIN/MAX instructions for XTheadVector [44/65] target/riscv: Add floating-point sign-injection instructions for XTheadVector [45/65] target/riscv: Add floating-point compare instructions for XTheadVector [46/65] target/riscv: Add floating-point classify and merge instructions for XTheadVector [47/65] target/riscv: Add single-width floating-point/integer type-convert instructions for XTheadV… [48/65] target/riscv: Add widening floating-point/integer type-convert instructions for XTheadVector [49/65] target/riscv: Add narrowing floating-point/integer type-convert instructions for XTheadVect… [50/65] target/riscv: Add single-width integer reduction instructions for XTheadVector [51/65] target/riscv: Add widening integer reduction instructions for XTheadVector [52/65] target/riscv: Add single-width floating-point reduction instructions for XTheadVector [53/65] target/riscv: Add widening floating-point reduction instructions for XTheadVector [54/65] target/riscv: Add mask-register logical instructions for XTheadVector [55/65] target/riscv: Add vector mask population count vmpopc for XTheadVector [56/65] target/riscv: Add th.vmfirst.m for XTheadVector [57/65] target/riscv: Add set-X-first mask bit instructrions for XTheadVector [58/65] target/riscv: Add vector iota instruction for XTheadVector [59/65] target/riscv: Add vector element index instruction for XTheadVector [60/65] target/riscv: Add integer extract and scalar move instructions for XTheadVector [61/65] target/riscv: Add floating-point scalar move instructions for XTheadVector [62/65] target/riscv: Add vector slide instructions for XTheadVector [63/65] target/riscv: Add vector register gather instructions for XTheadVector [64/65] target/riscv: Add vector compress instruction for XTheadVector [65/65] target/riscv: Enable XTheadVector extension for c906

diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6254be771f..04bd363ac0 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1996,3 +1996,19 @@ DEF_HELPER_6(th_vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(th_vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfadd_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfadd_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfadd_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc index 108f3249d0..a18c661f24 100644 --- a/target/riscv/insn_trans/trans_xtheadvector.c.inc +++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc @@ -1746,17 +1746,120 @@ GEN_OPIVX_NARROW_TRANS_TH(th_vnclip_vx) GEN_OPIVI_NARROW_TRANS_TH(th_vnclipu_vi, IMM_ZX, th_vnclipu_vx) GEN_OPIVI_NARROW_TRANS_TH(th_vnclip_vi, IMM_ZX, th_vnclip_vx) +/* + * Vector Float Point Arithmetic Instructions + */ + +/* Vector Single-Width Floating-Point Add/Subtract Instructions */ + +/* + * If the current SEW does not correspond to a supported IEEE floating-point + * type, an illegal instruction exception is raised. + */ +static bool opfvv_check_th(DisasContext *s, arg_rmrr *a) +{ + return require_xtheadvector(s) && + vext_check_isa_ill(s) && + th_check_overlap_mask(s, a->rd, a->vm, false) && + th_check_reg(s, a->rd, false) && + th_check_reg(s, a->rs2, false) && + th_check_reg(s, a->rs1, false) && + (s->sew != 0); +} + +/* + * The macro below including GEN_OPFVV_TRANS_TH and GEN_OPFVF_TRANS_TH, + * are just changed the data encoding compared to RVV1.0. + */ + +/* OPFVV without GVEC IR */ +#define GEN_OPFVV_TRANS_TH(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_4_ptr * const fns[3] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + \ + data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA_TH, VM, a->vm); \ + data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), \ + vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + fns[s->sew - 1]); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFVV_TRANS_TH(th_vfadd_vv, opfvv_check_th) +GEN_OPFVV_TRANS_TH(th_vfsub_vv, opfvv_check_th) + +#define gen_helper_opfvf_th gen_helper_opfvf + +static bool opfvf_check_th(DisasContext *s, arg_rmrr *a) +{ +/* + * If the current SEW does not correspond to a supported IEEE floating-point + * type, an illegal instruction exception is raised + */ + return require_xtheadvector(s) && + vext_check_isa_ill(s) && + th_check_overlap_mask(s, a->rd, a->vm, false) && + th_check_reg(s, a->rd, false) && + th_check_reg(s, a->rs2, false) && + (s->sew != 0); +} + +/* + * OPFVF without GVEC IR + * + * XTheadVector has different process policy when FLEN < SEW from + * RVV1.0. In XTheadVector, when FLEN < SEW, the value in freg should + * be nanboxed, while in RVV1.0, this situation is reserved. + * However, RVF-only cpus always have values NaN-boxed to 64-bits, so + * we do not have to deal with this situation differently. We can just + * use the RVV function opfvf_trans + */ +#define GEN_OPFVF_TRANS_TH(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_opfvf_th *const fns[3] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA_TH, VM, a->vm); \ + data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul); \ + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ + fns[s->sew - 1], s); \ + } \ + return false; \ +} + +GEN_OPFVF_TRANS_TH(th_vfadd_vf, opfvf_check_th) +GEN_OPFVF_TRANS_TH(th_vfsub_vf, opfvf_check_th) +GEN_OPFVF_TRANS_TH(th_vfrsub_vf, opfvf_check_th) + #define TH_TRANS_STUB(NAME) \ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { \ return require_xtheadvector(s); \ } -TH_TRANS_STUB(th_vfadd_vv) -TH_TRANS_STUB(th_vfadd_vf) -TH_TRANS_STUB(th_vfsub_vv) -TH_TRANS_STUB(th_vfsub_vf) -TH_TRANS_STUB(th_vfrsub_vf) TH_TRANS_STUB(th_vfwadd_vv) TH_TRANS_STUB(th_vfwadd_vf) TH_TRANS_STUB(th_vfwadd_wv) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 262cb28824..3784096da2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2904,17 +2904,17 @@ GEN_VEXT_VF(vfsub_vf_h, 2) GEN_VEXT_VF(vfsub_vf_w, 4) GEN_VEXT_VF(vfsub_vf_d, 8) -static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s) +uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s) { return float16_sub(b, a, s); } -static uint32_t float32_rsub(uint32_t a, uint32_t b, float_status *s) +uint32_t float32_rsub(uint32_t a, uint32_t b, float_status *s) { return float32_sub(b, a, s); } -static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s) +uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s) { return float64_sub(b, a, s); } diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h index a42dc080ec..5f250ab7ba 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -340,4 +340,8 @@ uint8_t vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b); uint16_t vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, uint16_t b); uint32_t vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b); +uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s); +uint32_t float32_rsub(uint32_t a, uint32_t b, float_status *s); +uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s); + #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c index 2e97a95392..60811ca813 100644 --- a/target/riscv/xtheadvector_helper.c +++ b/target/riscv/xtheadvector_helper.c @@ -2590,3 +2590,109 @@ THCALL(TH_OPIVX2_RM, th_vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32) GEN_TH_VX_RM(th_vnclipu_vx_b, 1, 1, clearb_th) GEN_TH_VX_RM(th_vnclipu_vx_h, 2, 2, clearh_th) GEN_TH_VX_RM(th_vnclipu_vx_w, 4, 4, clearl_th) + +/* + * Vector Float Point Arithmetic Instructions + */ + +/* Vector Single-Width Floating-Point Add/Subtract Instructions */ + +/* + * Some functions or macros are just the same as RVV1.0. + * But it is not worthy to extract them from RVV1.0, so we just copy + * them. + */ +#define TH_OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)\ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ + CPURISCVState *env) \ +{ \ + TX1 s1 = *((T1 *)vs1 + HS1(i)); \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status); \ +} + +#define GEN_TH_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint32_t vlmax = th_maxsz(desc) / ESZ; \ + uint32_t mlen = th_mlen(desc); \ + uint32_t vm = th_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + VSTART_CHECK_EARLY_EXIT(env); \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !th_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, vs1, vs2, i, env); \ + } \ + env->vstart = 0; \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ +} + +THCALL(TH_OPFVV2, th_vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add) +THCALL(TH_OPFVV2, th_vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add) +THCALL(TH_OPFVV2, th_vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add) +GEN_TH_VV_ENV(th_vfadd_vv_h, 2, 2, clearh_th) +GEN_TH_VV_ENV(th_vfadd_vv_w, 4, 4, clearl_th) +GEN_TH_VV_ENV(th_vfadd_vv_d, 8, 8, clearq_th) + +#define TH_OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ + CPURISCVState *env) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\ +} + +#define GEN_TH_VF(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint32_t vlmax = th_maxsz(desc) / ESZ; \ + uint32_t mlen = th_mlen(desc); \ + uint32_t vm = th_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + VSTART_CHECK_EARLY_EXIT(env); \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !th_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, s1, vs2, i, env); \ + } \ + env->vstart = 0; \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ +} + +THCALL(TH_OPFVF2, th_vfadd_vf_h, OP_UUU_H, H2, H2, float16_add) +THCALL(TH_OPFVF2, th_vfadd_vf_w, OP_UUU_W, H4, H4, float32_add) +THCALL(TH_OPFVF2, th_vfadd_vf_d, OP_UUU_D, H8, H8, float64_add) +GEN_TH_VF(th_vfadd_vf_h, 2, 2, clearh_th) +GEN_TH_VF(th_vfadd_vf_w, 4, 4, clearl_th) +GEN_TH_VF(th_vfadd_vf_d, 8, 8, clearq_th) + +THCALL(TH_OPFVV2, th_vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub) +THCALL(TH_OPFVV2, th_vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub) +THCALL(TH_OPFVV2, th_vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub) +GEN_TH_VV_ENV(th_vfsub_vv_h, 2, 2, clearh_th) +GEN_TH_VV_ENV(th_vfsub_vv_w, 4, 4, clearl_th) +GEN_TH_VV_ENV(th_vfsub_vv_d, 8, 8, clearq_th) +THCALL(TH_OPFVF2, th_vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub) +THCALL(TH_OPFVF2, th_vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub) +THCALL(TH_OPFVF2, th_vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub) +GEN_TH_VF(th_vfsub_vf_h, 2, 2, clearh_th) +GEN_TH_VF(th_vfsub_vf_w, 4, 4, clearl_th) +GEN_TH_VF(th_vfsub_vf_d, 8, 8, clearq_th) + +THCALL(TH_OPFVF2, th_vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub) +THCALL(TH_OPFVF2, th_vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub) +THCALL(TH_OPFVF2, th_vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub) +GEN_TH_VF(th_vfrsub_vf_h, 2, 2, clearh_th) +GEN_TH_VF(th_vfrsub_vf_w, 4, 4, clearl_th) +GEN_TH_VF(th_vfrsub_vf_d, 8, 8, clearq_th)

[36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector

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