diff mbox series

[3/5] target/riscv: Add a config option for native debug

Message ID 20211029152535.2055096-4-bin.meng@windriver.com
State Superseded
Headers show
Series target/riscv: Initial support for native debug feature via M-mode CSRs | expand

Commit Message

Bin Meng Oct. 29, 2021, 3:25 p.m. UTC 
Add a config option to enable support for native M-mode debug.
This is enabled by default and can be disabled with 'debug=false'.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 target/riscv/cpu.h | 2 ++
 target/riscv/cpu.c | 5 +++++
 2 files changed, 7 insertions(+)

Comments

Richard Henderson Oct. 29, 2021, 7:34 p.m. UTC | #1 
On 10/29/21 8:25 AM, Bin Meng wrote:
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eface73e7d..3a2fa97098 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -439,6 +439,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>           }
>       }
>   
> +    if (cpu->cfg.debug) {
> +        set_feature(env, RISCV_FEATURE_DEBUG);
> +    }
> +
>       set_resetvec(env, cpu->cfg.resetvec);
>   
>       /* Validate that MISA_MXL is set properly. */
> @@ -619,6 +623,7 @@ static Property riscv_cpu_properties[] = {
>       DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>       DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>       DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> +    DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>   
>       DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),

This half of the patch needs to come as the last patch, after you've finished 
implementation.  The first two hunks might as well fold into the first patch.


r~
diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 457adde952..5787d1598c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -74,6 +74,7 @@  enum {
     RISCV_FEATURE_MMU,
     RISCV_FEATURE_PMP,
     RISCV_FEATURE_EPMP,
+    RISCV_FEATURE_DEBUG,
     RISCV_FEATURE_MISA
 };
 
@@ -314,6 +315,7 @@  struct RISCVCPU {
         bool mmu;
         bool pmp;
         bool epmp;
+        bool debug;
         uint64_t resetvec;
     } cfg;
 };
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eface73e7d..3a2fa97098 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -439,6 +439,10 @@  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         }
     }
 
+    if (cpu->cfg.debug) {
+        set_feature(env, RISCV_FEATURE_DEBUG);
+    }
+
     set_resetvec(env, cpu->cfg.resetvec);
 
     /* Validate that MISA_MXL is set properly. */
@@ -619,6 +623,7 @@  static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+    DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
 
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),