| Message ID | 20210805175626.11573-4-ruinland@andestech.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add basic support for custom CSR | expand |
On Fri, Aug 6, 2021 at 2:00 AM Ruinland Chuan-Tzu Tsai <ruinland@andestech.com> wrote: > > From: Ruinalnd ChuanTzu Tsai <ruinland@andestech.com> > > Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without The latest RISC-V core from Andes is AX45 and A45. Should we just support the latest one? > enhanced features (yet). > > Signed-off-by: Dylan Jhong <dylan@andestech.com> > --- > target/riscv/cpu.c | 16 ++++++++++++++++ > target/riscv/cpu.h | 2 ++ > 2 files changed, 18 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 3a638b5..9eb1e3a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -182,6 +182,13 @@ static void rv64_base_cpu_init(Object *obj) > set_misa(env, RV64); > } > > +static void ax25_cpu_init(Object *obj) nits: for name consistency, should be rv64_andes_ax25_cpu_init() > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > + > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -235,6 +242,13 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_resetvec(env, DEFAULT_RSTVEC); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > + > +static void a25_cpu_init(Object *obj) nits: rv32_andes_a25_cpu_init() > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > #endif > > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > @@ -726,8 +740,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_A25, a25_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > #endif > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 52df9bb..bd79d63 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -37,6 +37,8 @@ > #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > +#define TYPE_RISCV_CPU_A25 RISCV_CPU_TYPE_NAME("andes-a25") > +#define TYPE_RISCV_CPU_AX25 RISCV_CPU_TYPE_NAME("andes-ax25") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") Regards, Bin
Hi Bin and Alistair, >> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without > The latest RISC-V core from Andes is AX45 and A45. Should we just > support the latest one? Maybe we can have them all ? AX25 and A25 is still in production, and we still have new clients using these CPU models. >> +static void ax25_cpu_init(Object *obj) >nits: for name consistency, should be rv64_andes_ax25_cpu_init() Will do. >> +static void a25_cpu_init(Object *obj) >nits: rv32_andes_a25_cpu_init() Will do. > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > #endif > > Regards, > Bin My sincere regards, Ruinland CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.
On Fri, Aug 6, 2021 at 2:12 PM Ruinland Chuan-Tzu Tsa(蔡傳資) <ruinland@andestech.com> wrote: > > Hi Bin and Alistair, > > >> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without > > > The latest RISC-V core from Andes is AX45 and A45. Should we just > > support the latest one? > > Maybe we can have them all ? > AX25 and A25 is still in production, and we still have new clients using these CPU models. > Does AX25 and AX45 have any significant difference? Regards, Bin
On Fri, Aug 6, 2021 at 7:51 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Fri, Aug 6, 2021 at 2:12 PM Ruinland Chuan-Tzu Tsa(蔡傳資) > <ruinland@andestech.com> wrote: > > > > Hi Bin and Alistair, > > > > >> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without > > > > > The latest RISC-V core from Andes is AX45 and A45. Should we just > > > support the latest one? > > > > Maybe we can have them all ? > > AX25 and A25 is still in production, and we still have new clients using these CPU models. > > > > Does AX25 and AX45 have any significant difference? My hope is that the way the custom CSRs are implemented means that the Andes CPUs can be self contained. That way QEMU can support whatever Andes upstreams and it shouldn't add a maintenance burden on anyone else. Starting with a AX25 is fine with me. Whatever Andes is willing to upstream, maintain and test works for me. Alistair > > Regards, > Bin >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3a638b5..9eb1e3a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -182,6 +182,13 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, RV64); } +static void ax25_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); +} + static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -235,6 +242,13 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } + +static void a25_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); +} #endif static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -726,8 +740,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_A25, a25_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 52df9bb..bd79d63 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -37,6 +37,8 @@ #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_A25 RISCV_CPU_TYPE_NAME("andes-a25") +#define TYPE_RISCV_CPU_AX25 RISCV_CPU_TYPE_NAME("andes-ax25") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")