Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1748 patches
« 1 2 3 4 … 17 18 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PATCH-4.2,v1,1/6] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - - - - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,2/6] target/riscv: Remove strict perm checking for CSR R/W RISC-V: Hypervisor prep work part 2 - - - - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,3/6] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - - 3 - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,4/6] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - - 2 - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,5/6] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - - - - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v1,6/6] target/riscv: Fix Floating Point register names RISC-V: Hypervisor prep work part 2 - - - - --- 2019-07-25 Alistair Francis New
[PATCH-4.2,v2,1/5] target/riscv: Don't set write permissions on dirty PTEs RISC-V: Hypervisor prep work part 2 - - - - --- 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,2/5] riscv: plic: Remove unused interrupt functions RISC-V: Hypervisor prep work part 2 - - 3 - --- 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,3/5] target/riscv: Create function to test if FP is enabled RISC-V: Hypervisor prep work part 2 - - 2 - --- 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,4/5] target/riscv: Update the Hypervisor CSRs to v0.4 RISC-V: Hypervisor prep work part 2 - - - - --- 2019-07-30 Alistair Francis New
[PATCH-4.2,v2,5/5] target/riscv: Fix Floating Point register names RISC-V: Hypervisor prep work part 2 - - - - --- 2019-07-30 Alistair Francis New
[PULL,0/1] Register API Queue - - - - --- 2020-05-05 Alistair Francis New
[PULL,0/1] register-api queue - - - - --- 2020-05-27 Alistair Francis New
[PULL,0/2] register queue - - - - --- 2020-09-27 Alistair Francis New
[PULL,0/2] riscv-to-apply queue - - - - --- 2020-11-14 Alistair Francis New
[PULL,0/5] riscv-to-apply queue - - - - --- 2020-07-22 Alistair Francis New
[PULL,0/6] riscv-to-apply queue - - - - --- 2020-11-10 Alistair Francis New
[PULL,0/7] riscv-to-apply queue - - - - --- 2021-06-24 Alistair Francis New
[PULL,00/11] riscv-to-apply queue - - - - --- 2021-07-12 Alistair Francis New
[PULL,00/12] riscv-to-apply queue - - - - --- 2021-01-17 Alistair Francis New
[PULL,00/12] riscv-to-apply queue - - - - --- 2020-10-23 Alistair Francis New
[PULL,00/14] RISC-V Patch Queue for 5.1 - - - - --- 2020-04-29 Alistair Francis New
[PULL,00/15] riscv-to-apply queue - - - - --- 2020-07-14 Alistair Francis New
[PULL,00/15] riscv-to-apply queue - - - - --- 2020-06-03 Alistair Francis New
[PULL,00/16] riscv-to-apply queue - - - - --- 2021-03-23 Alistair Francis New
[PULL,00/18] riscv-to-apply queue - - - - --- 2020-10-29 Alistair Francis New
[PULL,00/18] riscv-to-apply queue - - - - --- 2020-08-25 Alistair Francis New
[PULL,00/19] riscv-to-apply queue - - - - --- 2021-02-18 Alistair Francis New
[PULL,00/20] riscv-to-apply queue - - - - --- 2020-08-12 Alistair Francis New
[PULL,00/23] riscv-to-apply queue - - - - --- 2020-12-18 Alistair Francis New
[PULL,00/30] riscv-to-apply queue - - - - --- 2020-09-10 Alistair Francis New
[PULL,00/30] riscv-to-apply queue - - - - --- 2020-09-10 Alistair Francis New
[PULL,00/32] riscv-to-apply queue - - - - --- 2021-06-08 Alistair Francis New
[PULL,00/32] riscv-to-apply queue - - - - --- 2020-06-19 Alistair Francis New
[PULL,00/42] riscv-to-apply queue - - - - --- 2021-05-03 Alistair Francis New
[PULL,00/63] riscv-to-apply queue - - - - --- 2020-06-26 Alistair Francis New
[PULL,01/10] hw/riscv/virt: Increase the number of interrupts riscv-pullreq queue - - - - --- 2018-10-11 Alistair Francis New
[PULL,01/11] target/riscv: pmp: Fix some typos [PULL,01/11] target/riscv: pmp: Fix some typos - - 2 - --- 2021-07-12 Alistair Francis New
[PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 2 - --- 2021-01-17 Alistair Francis New
[PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 1 - --- 2020-10-23 Alistair Francis New
[PULL,01/14] riscv/sifive_u: Fix up file ordering [PULL,01/14] riscv/sifive_u: Fix up file ordering - - 1 - --- 2020-04-29 Alistair Francis New
[PULL,01/15] MAINTAINERS: Add an entry for OpenSBI firmware [PULL,01/15] MAINTAINERS: Add an entry for OpenSBI firmware - - 1 - --- 2020-07-14 Alistair Francis New
[PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - - 1 - --- 2020-06-03 Alistair Francis New
[PULL,01/16] target/riscv: fix vs() to return proper error code [PULL,01/16] target/riscv: fix vs() to return proper error code - - 2 - --- 2021-03-23 Alistair Francis New
[PULL,01/18] hw/riscv: Allow creating multiple instances of CLINT [PULL,01/18] hw/riscv: Allow creating multiple instances of CLINT - - 2 - --- 2020-08-25 Alistair Francis New
[PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,01/19] target/riscv: Declare csr_ops[] with a known size [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-02-18 Alistair Francis New
[PULL,01/20] target/riscv: Generate nanboxed results from fp helpers [PULL,01/20] target/riscv: Generate nanboxed results from fp helpers - - 1 - --- 2020-08-12 Alistair Francis New
[PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 1 - --- 2020-09-10 Alistair Francis New
[PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - - 2 - --- 2020-06-19 Alistair Francis New
[PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,01/63] riscv: plic: Honour source priorities [PULL,01/63] riscv: plic: Honour source priorities - - 1 - --- 2020-06-26 Alistair Francis New
[PULL,02/10] hw/riscv/virt: Connect the gpex PCIe riscv-pullreq queue - - - - --- 2018-10-11 Alistair Francis New
[PULL,02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 1 - --- 2021-01-17 Alistair Francis New
[PULL,02/12] hw/intc: Move sifive_plic.h to the include directory [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - 1 2 - --- 2020-10-23 Alistair Francis New
[PULL,02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC [PULL,01/14] riscv/sifive_u: Fix up file ordering - - 1 1 --- 2020-04-29 Alistair Francis New
[PULL,02/15] hw/riscv: virt: Sort the SoC memmap table entries [PULL,01/15] MAINTAINERS: Add an entry for OpenSBI firmware - - 1 - --- 2020-07-14 Alistair Francis New
[PULL,02/15] riscv: Change the default behavior if no -bios option is specified [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - - 1 - --- 2020-06-03 Alistair Francis New
[PULL,02/16] hw/char: disable ibex uart receive if the buffer is full [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,02/18] hw/riscv: Allow creating multiple instances of PLIC [PULL,01/18] hw/riscv: Allow creating multiple instances of CLINT - - 2 - --- 2020-08-25 Alistair Francis New
[PULL,02/18] hw/riscv: virt: Allow passing custom DTB [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-02-18 Alistair Francis New
[PULL,02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s [PULL,01/20] target/riscv: Generate nanboxed results from fp helpers - - 1 - --- 2020-08-12 Alistair Francis New
[PULL,02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 1 - --- 2020-12-18 Alistair Francis New
[PULL,02/30] riscv: sifive_test: Allow 16-bit writes to memory region [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap 1 2 1 - --- 2020-09-10 Alistair Francis New
[PULL,02/32] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,02/32] sifive_e: Support the revB machine [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - - - - --- 2020-06-19 Alistair Francis New
[PULL,02/42] docs/system/generic-loader.rst: Fix style [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 1 - --- 2021-05-03 Alistair Francis New
[PULL,02/63] riscv: plic: Add a couple of mising sifive_plic_update calls [PULL,01/63] riscv: plic: Honour source priorities - - 1 - --- 2020-06-26 Alistair Francis New
[PULL,03/10] riscv: Enable VGA and PCIE_VGA riscv-pullreq queue - - - - --- 2018-10-11 Alistair Francis New
[PULL,03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,03/12] gdb: riscv: Add target description [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 3 - --- 2021-01-17 Alistair Francis New
[PULL,03/12] target/riscv: Fix update of hstatus.SPVP [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 1 - --- 2020-10-23 Alistair Francis New
[PULL,03/14] riscv/sifive_u: Add a serial property to the sifive_u machine [PULL,01/14] riscv/sifive_u: Fix up file ordering - - 2 - --- 2020-04-29 Alistair Francis New
[PULL,03/15] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - - 2 - --- 2020-06-03 Alistair Francis New
[PULL,03/15] riscv: Unify Qemu's reset vector code path [PULL,01/15] MAINTAINERS: Add an entry for OpenSBI firmware - - 2 1 --- 2020-07-14 Alistair Francis New
[PULL,03/16] target/riscv: propagate PMP permission to TLB page [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,03/18] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines [PULL,01/18] hw/riscv: Allow creating multiple instances of CLINT - - 1 - --- 2020-08-25 Alistair Francis New
[PULL,03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
[PULL,03/19] roms/opensbi: Upgrade from v0.8 to v0.9 [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c [PULL,01/20] target/riscv: Generate nanboxed results from fp helpers - - 1 - --- 2020-08-12 Alistair Francis New
[PULL,03/23] hw/core/register.c: Don't use '#' flag of printf format [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,03/30] target/riscv: cpu: Add a new 'resetvec' property [PULL,01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap - - 2 - --- 2020-09-10 Alistair Francis New
[PULL,03/32] hw/riscv: Support the official CLINT DT bindings [PULL,01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper - - 1 - --- 2021-06-08 Alistair Francis New
[PULL,03/32] riscv: Generalize CPU init routine for the base CPU [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - - 1 - --- 2020-06-19 Alistair Francis New
[PULL,03/42] target/riscv: Align the data type of reset vector address [PULL,01/42] target/riscv: Remove privilege v1.9 specific CSR related code - - 2 - --- 2021-05-03 Alistair Francis New
[PULL,03/63] target/riscv: add vector extension field in CPURISCVState [PULL,01/63] riscv: plic: Honour source priorities 1 - 1 - --- 2020-06-26 Alistair Francis New
[PULL,04/10] hw/riscv/sifive_u: Connect the Xilinx PCIe riscv-pullreq queue - - - - --- 2018-10-11 Alistair Francis New
[PULL,04/11] docs/system: riscv: Add documentation for virt machine [PULL,01/11] target/riscv: pmp: Fix some typos - - 1 - --- 2021-07-12 Alistair Francis New
[PULL,04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 1 1 --- 2021-01-17 Alistair Francis New
[PULL,04/12] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt [PULL,01/12] riscv: Convert interrupt logs to use qemu_log_mask() - - 1 - --- 2020-10-23 Alistair Francis New
[PULL,04/14] riscv: Don't use stage-2 PTE lookup protection flags [PULL,01/14] riscv/sifive_u: Fix up file ordering - - 1 1 --- 2020-04-29 Alistair Francis New
[PULL,04/15] RISC-V: Copy the fdt in dram instead of ROM [PULL,01/15] MAINTAINERS: Add an entry for OpenSBI firmware - - 2 1 --- 2020-07-14 Alistair Francis New
[PULL,04/15] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - - 2 - --- 2020-06-03 Alistair Francis New
[PULL,04/16] target/riscv: add log of PMP permission checking [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,04/18] hw/riscv: spike: Allow creating multiple NUMA sockets [PULL,01/18] hw/riscv: Allow creating multiple instances of CLINT - - 1 - --- 2020-08-25 Alistair Francis New
[PULL,04/18] target/riscv: Add basic vmstate description of CPU [PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB - - 1 - --- 2020-10-29 Alistair Francis New
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