Show patches with: Series = [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB       |    State = Action Required       |    Archived = No       |   23 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,23/23] riscv/opentitan: Update the OpenTitan memory layout [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - - - --- 2020-12-18 Alistair Francis New
[PULL,22/23] hw/riscv: Use the CPU to determine if 32-bit [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,21/23] target/riscv: cpu: Set XLEN independently from target [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,20/23] target/riscv: csr: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,19/23] target/riscv: cpu_helper: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 3 1 --- 2020-12-18 Alistair Francis New
[PULL,18/23] target/riscv: cpu: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 3 1 --- 2020-12-18 Alistair Francis New
[PULL,17/23] target/riscv: Specify the XLEN for CPUs [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 3 1 --- 2020-12-18 Alistair Francis New
[PULL,16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,15/23] target/riscv: fpu_helper: Match function defs in HELPER macros [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - - - --- 2020-12-18 Alistair Francis New
[PULL,14/23] hw/riscv: sifive_u: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,13/23] hw/riscv: spike: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 - --- 2020-12-18 Alistair Francis New
[PULL,12/23] hw/riscv: virt: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,11/23] hw/riscv: boot: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,10/23] riscv: virt: Remove target macro conditionals [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,09/23] riscv: spike: Remove target macro conditionals [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 - --- 2020-12-18 Alistair Francis New
[PULL,08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,07/23] hw/riscv: Expand the is 32-bit check to support more CPUs [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 1 - --- 2020-12-18 Alistair Francis New
[PULL,06/23] intc/ibex_plic: Clear interrupts that occur during claim process [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - - 1 --- 2020-12-18 Alistair Francis New
[PULL,05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,04/23] target/riscv: Fix the bug of HLVX/HLV/HSV [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,03/23] hw/core/register.c: Don't use '#' flag of printf format [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 1 - --- 2020-12-18 Alistair Francis New
[PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New