Show patches with: Submitter = Bin Meng       |   1259 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
riscv: rv32: Root page table address can be larger than 32-bit riscv: rv32: Root page table address can be larger than 32-bit - - - - --- 2019-07-31 Bin Meng Superseded
riscv: hmp: Add a command to show virtual memory mappings riscv: hmp: Add a command to show virtual memory mappings 1 - 1 - --- 2019-07-31 Bin Meng Superseded
hw: net: cadence_gem: Fix build errors in DB_PRINT() hw: net: cadence_gem: Fix build errors in DB_PRINT() - - - - --- 2019-08-05 Bin Meng Superseded
[01/28] riscv: hw: Remove superfluous "linux, phandle" property riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-05 Bin Meng Superseded
[02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-05 Bin Meng Superseded
[03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-05 Bin Meng Superseded
[04/28] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[05/28] riscv: hart: Support heterogeneous harts population riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[07/28] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[08/28] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-05 Bin Meng Superseded
[09/28] riscv: sifive_u: Update UART base addresses riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 1 - --- 2019-08-05 Bin Meng Superseded
[10/28] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-05 Bin Meng Superseded
[11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - - - --- 2019-08-05 Bin Meng Superseded
[13/28] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[14/28] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[16/28] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[17/28] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-05 Bin Meng Superseded
[18/28] riscv: hw: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[21/28] riscv: sifive_u: Update UART and ethernet node clock properties riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[22/28] riscv: sifive_u: Generate an aliases node in the device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[24/28] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[25/28] riscv: sifive_u: Support loading initramfs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[26/28] riscv: hw: Update PLIC device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-05 Bin Meng Superseded
[27/28] riscv: virt: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-05 Bin Meng Superseded
[28/28] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-05 Bin Meng Superseded
[v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-07 Bin Meng Superseded
[v2,02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-07 Bin Meng Superseded
[v2,03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - --- 2019-08-07 Bin Meng Superseded
[v2,04/28] riscv: hart: Extract hart realize to a separate routine [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,05/28] riscv: hart: Support heterogeneous harts population [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,07/28] riscv: sifive_u: Set the minimum number of cpus to 2 [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,08/28] riscv: sifive_u: Update PLIC hart topology configuration string [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-07 Bin Meng Superseded
[v2,09/28] riscv: sifive_u: Update UART base addresses [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property 1 - 2 - --- 2019-08-07 Bin Meng Superseded
[v2,10/28] riscv: sifive_u: Remove the unnecessary include of prci header [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-07 Bin Meng Superseded
[v2,11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-07 Bin Meng Superseded
[v2,12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property 1 - 2 - --- 2019-08-07 Bin Meng Superseded
[v2,13/28] riscv: sifive_e: prci: Update the PRCI register block size [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,14/28] riscv: sifive: Implement PRCI model for FU540 [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,16/28] riscv: sifive_u: Add PRCI block to the SoC [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,17/28] riscv: sifive_u: Change UART node name in device tree [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-07 Bin Meng Superseded
[v2,18/28] riscv: hw: Implement a model for SiFive FU540 OTP [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,19/28] riscv: sifive_u: Instantiate OTP memory with a serial number [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,21/28] riscv: sifive_u: Update UART and ethernet node clock properties [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,22/28] riscv: sifive_u: Generate an aliases node in the device tree [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,23/28] riscv: sifive_u: Fix broken GEM support [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - - - --- 2019-08-07 Bin Meng Superseded
[v2,24/28] riscv: sifive_u: Support loading initramfs [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-07 Bin Meng Superseded
[v2,25/28] riscv: hw: Remove not needed PLIC properties in device tree [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-07 Bin Meng Superseded
[v2,27/28] riscv: virt: Change create_fdt() to return void [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 2 - --- 2019-08-07 Bin Meng Superseded
[v2,28/28] riscv: sifive_u: Update model and compatible strings in device tree [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-07 Bin Meng Superseded
[v2] riscv: hmp: Add a command to show virtual memory mappings [v2] riscv: hmp: Add a command to show virtual memory mappings 1 - - - --- 2019-08-08 Bin Meng Superseded
[v2] hw: net: cadence_gem: Fix build errors in DB_PRINT() [v2] hw: net: cadence_gem: Fix build errors in DB_PRINT() - - - - --- 2019-08-08 Bin Meng Superseded
[v3,01/28] riscv: hw: Remove superfluous "linux, phandle" property riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,04/28] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,05/28] riscv: hart: Support heterogeneous harts population riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,07/28] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,08/28] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,09/28] riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,10/28] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,13/28] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,14/28] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,16/28] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,17/28] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,18/28] riscv: hw: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,19/28] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,21/28] riscv: sifive_u: Update UART and ethernet node clock properties riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-11 Bin Meng Superseded
[v3,22/28] riscv: sifive_u: Generate an aliases node in the device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,23/28] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3,24/28] riscv: sifive_u: Support loading initramfs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,25/28] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-11 Bin Meng Superseded
[v3,27/28] riscv: virt: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 3 - --- 2019-08-11 Bin Meng Superseded
[v3,28/28] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-11 Bin Meng Superseded
[v3] riscv: hmp: Add a command to show virtual memory mappings [v3] riscv: hmp: Add a command to show virtual memory mappings 1 - - - --- 2019-08-12 Bin Meng Superseded
[v4,01/28] riscv: hw: Remove superfluous "linux, phandle" property [v4,01/28] riscv: hw: Remove superfluous "linux, phandle" property - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,03/28] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-19 Bin Meng Superseded
[v4,04/28] riscv: hw: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 3 - --- 2019-08-19 Bin Meng Superseded
[v4,06/28] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-08-19 Bin Meng Superseded
[v4,09/28] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-19 Bin Meng Superseded
[v4,11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-08-19 Bin Meng Superseded
[v4,12/28] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-19 Bin Meng Superseded
[v4,14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,15/28] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,16/28] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
[v4,17/28] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - - - --- 2019-08-19 Bin Meng Superseded
[v4,18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-08-19 Bin Meng Superseded
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