diff mbox series

[v5,11/11] RISC-V: Table A.6 conformance tests

Message ID 20230427162301.1151333-12-patrick@rivosinc.com
State New
Headers show
Series RISC-V: Implement ISA Manual Table A.6 Mappings | expand

Commit Message

Patrick O'Neill April 27, 2023, 4:23 p.m. UTC 
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.

2023-04-27 Patrick O'Neill <patrick@rivosinc.com>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test.
	* gcc.target/riscv/amo-table-a-6-amo-add-2.c: New test.
	* gcc.target/riscv/amo-table-a-6-amo-add-3.c: New test.
	* gcc.target/riscv/amo-table-a-6-amo-add-4.c: New test.
	* gcc.target/riscv/amo-table-a-6-amo-add-5.c: New test.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: New test.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: New test.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: New test.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: New test.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: New test.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: New test.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: New test.
	* gcc.target/riscv/amo-table-a-6-fence-1.c: New test.
	* gcc.target/riscv/amo-table-a-6-fence-2.c: New test.
	* gcc.target/riscv/amo-table-a-6-fence-3.c: New test.
	* gcc.target/riscv/amo-table-a-6-fence-4.c: New test.
	* gcc.target/riscv/amo-table-a-6-fence-5.c: New test.
	* gcc.target/riscv/amo-table-a-6-load-1.c: New test.
	* gcc.target/riscv/amo-table-a-6-load-2.c: New test.
	* gcc.target/riscv/amo-table-a-6-load-3.c: New test.
	* gcc.target/riscv/amo-table-a-6-store-1.c: New test.
	* gcc.target/riscv/amo-table-a-6-store-2.c: New test.
	* gcc.target/riscv/amo-table-a-6-store-compat-3.c: New test.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: New test.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: New test.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: New test.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: New test.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: New test.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 .../gcc.target/riscv/amo-table-a-6-amo-add-1.c        |  8 ++++++++
 .../gcc.target/riscv/amo-table-a-6-amo-add-2.c        |  8 ++++++++
 .../gcc.target/riscv/amo-table-a-6-amo-add-3.c        |  8 ++++++++
 .../gcc.target/riscv/amo-table-a-6-amo-add-4.c        |  8 ++++++++
 .../gcc.target/riscv/amo-table-a-6-amo-add-5.c        |  8 ++++++++
 .../riscv/amo-table-a-6-compare-exchange-1.c          | 10 ++++++++++
 .../riscv/amo-table-a-6-compare-exchange-2.c          | 10 ++++++++++
 .../riscv/amo-table-a-6-compare-exchange-3.c          | 10 ++++++++++
 .../riscv/amo-table-a-6-compare-exchange-4.c          | 10 ++++++++++
 .../riscv/amo-table-a-6-compare-exchange-5.c          | 10 ++++++++++
 .../riscv/amo-table-a-6-compare-exchange-6.c          | 11 +++++++++++
 .../riscv/amo-table-a-6-compare-exchange-7.c          | 10 ++++++++++
 .../gcc.target/riscv/amo-table-a-6-fence-1.c          |  8 ++++++++
 .../gcc.target/riscv/amo-table-a-6-fence-2.c          | 10 ++++++++++
 .../gcc.target/riscv/amo-table-a-6-fence-3.c          | 10 ++++++++++
 .../gcc.target/riscv/amo-table-a-6-fence-4.c          | 10 ++++++++++
 .../gcc.target/riscv/amo-table-a-6-fence-5.c          | 10 ++++++++++
 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c |  9 +++++++++
 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c | 11 +++++++++++
 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c | 11 +++++++++++
 .../gcc.target/riscv/amo-table-a-6-store-1.c          |  9 +++++++++
 .../gcc.target/riscv/amo-table-a-6-store-2.c          | 11 +++++++++++
 .../gcc.target/riscv/amo-table-a-6-store-compat-3.c   | 11 +++++++++++
 .../riscv/amo-table-a-6-subword-amo-add-1.c           |  9 +++++++++
 .../riscv/amo-table-a-6-subword-amo-add-2.c           |  9 +++++++++
 .../riscv/amo-table-a-6-subword-amo-add-3.c           |  9 +++++++++
 .../riscv/amo-table-a-6-subword-amo-add-4.c           |  9 +++++++++
 .../riscv/amo-table-a-6-subword-amo-add-5.c           |  9 +++++++++
 28 files changed, 266 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c

Comments

Jeff Law April 28, 2023, 6:07 p.m. UTC | #1 
On 4/27/23 10:23, Patrick O'Neill wrote:
> These tests cover basic cases to ensure the atomic mappings follow the
> strengthened Table A.6 mappings that are compatible with Table A.7.
> 
> 2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-amo-add-2.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-amo-add-3.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-amo-add-4.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-amo-add-5.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-fence-1.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-fence-2.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-fence-3.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-fence-4.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-fence-5.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-load-1.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-load-2.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-load-3.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-store-1.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-store-2.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-store-compat-3.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: New test.
> 	* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: New test.
OK.  And as mentioned earlier, there is a framework where you can verify 
ordering as well.  Your call whether or not you want to switch to that 
form.  If you do choose to checking ordering, consider that patch 
pre-approved.

Jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
new file mode 100644
index 00000000000..cb044f78fcf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* Verify that atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler "amoadd.w\t" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
new file mode 100644
index 00000000000..c8445321989
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* Verify that atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler "amoadd.w.aq\t" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
new file mode 100644
index 00000000000..dfec3020c91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* Verify that atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler "amoadd.w.rl\t" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
new file mode 100644
index 00000000000..b9f90e199b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* Verify that atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
new file mode 100644
index 00000000000..94c4bec933b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* Verify that atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
new file mode 100644
index 00000000000..a9141cde48f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
new file mode 100644
index 00000000000..b1ebb20e2f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME, __ATOMIC_CONSUME);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
new file mode 100644
index 00000000000..47d8d02f7e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
new file mode 100644
index 00000000000..af6e1d69c75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
new file mode 100644
index 00000000000..ceb5660b6af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
new file mode 100644
index 00000000000..7b012fb1288
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
@@ -0,0 +1,11 @@ 
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
+/* Mixed mappings need to be unioned.  */
+/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
new file mode 100644
index 00000000000..5adec6f7a19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+  __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
new file mode 100644
index 00000000000..b8c28013ef3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
new file mode 100644
index 00000000000..117f9036e39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
new file mode 100644
index 00000000000..4b6dd7a9aa7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
new file mode 100644
index 00000000000..d40d3bc37db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "fence.tso" 1 } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
new file mode 100644
index 00000000000..71f76c27789
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
new file mode 100644
index 00000000000..8278198072e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* Verify that load mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
new file mode 100644
index 00000000000..84b6cc542ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
@@ -0,0 +1,11 @@ 
+/* { dg-do compile } */
+/* Verify that load mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
new file mode 100644
index 00000000000..3f15041d117
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
@@ -0,0 +1,11 @@ 
+/* { dg-do compile } */
+/* Verify that load mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */
+/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
new file mode 100644
index 00000000000..c200bd1d11d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* Verify that store mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
new file mode 100644
index 00000000000..1cf366b5986
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
@@ -0,0 +1,11 @@ 
+/* { dg-do compile } */
+/* Verify that store mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
new file mode 100644
index 00000000000..288e1493156
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
@@ -0,0 +1,11 @@ 
+/* { dg-do compile } */
+/* Verify that store mapping are compatible with Table A.6 & A.7.  */
+/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */
+/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */
+/* { dg-final { scan-assembler-not "fence\tr,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
new file mode 100644
index 00000000000..9efa25ddf26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
+
+void
+foo (short* bar, short* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
new file mode 100644
index 00000000000..536f7e9228f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
+
+void
+foo (short* bar, short* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
new file mode 100644
index 00000000000..69c2324a1f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (short* bar, short* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
new file mode 100644
index 00000000000..a0779b4c421
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (short* bar, short* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
new file mode 100644
index 00000000000..f88901dc717
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
+/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
+/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
+
+void
+foo (short* bar, short* baz) {
+  __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST);
+}